1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s 3; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s 4 5define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) { 6; GFX10-LABEL: test_wave32: 7; GFX10: ; %bb.0: ; %entry 8; GFX10-NEXT: s_clause 0x1 9; GFX10-NEXT: s_load_dword s0, s[8:9], 0x0 10; GFX10-NEXT: s_load_dword s1, s[8:9], 0x24 11; GFX10-NEXT: s_waitcnt lgkmcnt(0) 12; GFX10-NEXT: s_cmp_eq_u32 s0, 0 13; GFX10-NEXT: s_cselect_b32 s0, 1, 0 14; GFX10-NEXT: s_and_b32 s0, 1, s0 15; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 16; GFX10-NEXT: s_or_b32 s0, s0, s1 17; GFX10-NEXT: v_mov_b32_e32 v0, s0 18; GFX10-NEXT: global_store_dword v[0:1], v0, off 19; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 20; GFX10-NEXT: s_endpgm 21; 22; GFX11-LABEL: test_wave32: 23; GFX11: ; %bb.0: ; %entry 24; GFX11-NEXT: s_clause 0x1 25; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0 26; GFX11-NEXT: s_load_b32 s1, s[4:5], 0x24 27; GFX11-NEXT: s_waitcnt lgkmcnt(0) 28; GFX11-NEXT: s_cmp_eq_u32 s0, 0 29; GFX11-NEXT: s_cselect_b32 s0, 1, 0 30; GFX11-NEXT: s_and_b32 s0, 1, s0 31; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 32; GFX11-NEXT: s_or_b32 s0, s0, s1 33; GFX11-NEXT: v_mov_b32_e32 v0, s0 34; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc 35; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 36; GFX11-NEXT: s_endpgm 37entry: 38 %cond = icmp eq i32 %arg0, 0 39 %break = call i32 @llvm.amdgcn.if.break.i32(i1 %cond, i32 %saved) 40 store volatile i32 %break, ptr addrspace(1) undef 41 ret void 42} 43 44declare i32 @llvm.amdgcn.if.break.i32(i1, i32) 45