1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) { 5; GCN-LABEL: test_wave64: 6; GCN: ; %bb.0: ; %entry 7; GCN-NEXT: s_load_dword s0, s[8:9], 0x0 8; GCN-NEXT: s_waitcnt lgkmcnt(0) 9; GCN-NEXT: s_cmp_lg_u32 s0, 0 10; GCN-NEXT: s_cbranch_scc1 .LBB0_2 11; GCN-NEXT: ; %bb.1: ; %mid 12; GCN-NEXT: v_mov_b32_e32 v0, 0 13; GCN-NEXT: global_store_dword v[0:1], v0, off 14; GCN-NEXT: s_waitcnt vmcnt(0) 15; GCN-NEXT: .LBB0_2: ; %bb 16; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8 17; GCN-NEXT: s_waitcnt lgkmcnt(0) 18; GCN-NEXT: s_or_b64 exec, exec, s[0:1] 19; GCN-NEXT: v_mov_b32_e32 v0, 0 20; GCN-NEXT: global_store_dword v[0:1], v0, off 21; GCN-NEXT: s_waitcnt vmcnt(0) 22; GCN-NEXT: s_endpgm 23entry: 24 %cond = icmp eq i32 %arg0, 0 25 br i1 %cond, label %mid, label %bb 26 27mid: 28 store volatile i32 0, ptr addrspace(1) undef 29 br label %bb 30 31bb: 32 call void @llvm.amdgcn.end.cf.i64(i64 %saved) 33 store volatile i32 0, ptr addrspace(1) undef 34 ret void 35} 36 37declare void @llvm.amdgcn.end.cf.i64(i64 %val) 38