1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s 3; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s 4 5define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) { 6; GFX10-LABEL: test_wave32: 7; GFX10: ; %bb.0: ; %entry 8; GFX10-NEXT: s_load_dword s0, s[8:9], 0x0 9; GFX10-NEXT: s_waitcnt lgkmcnt(0) 10; GFX10-NEXT: s_cmp_lg_u32 s0, 0 11; GFX10-NEXT: s_cbranch_scc1 .LBB0_2 12; GFX10-NEXT: ; %bb.1: ; %mid 13; GFX10-NEXT: v_mov_b32_e32 v0, 0 14; GFX10-NEXT: global_store_dword v[0:1], v0, off 15; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 16; GFX10-NEXT: .LBB0_2: ; %bb 17; GFX10-NEXT: s_load_dword s0, s[8:9], 0x24 18; GFX10-NEXT: s_waitcnt lgkmcnt(0) 19; GFX10-NEXT: s_waitcnt_depctr 0xffe3 20; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0 21; GFX10-NEXT: v_mov_b32_e32 v0, 0 22; GFX10-NEXT: global_store_dword v[0:1], v0, off 23; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 24; GFX10-NEXT: s_endpgm 25; 26; GFX11-LABEL: test_wave32: 27; GFX11: ; %bb.0: ; %entry 28; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0 29; GFX11-NEXT: s_waitcnt lgkmcnt(0) 30; GFX11-NEXT: s_cmp_lg_u32 s0, 0 31; GFX11-NEXT: s_cbranch_scc1 .LBB0_2 32; GFX11-NEXT: ; %bb.1: ; %mid 33; GFX11-NEXT: v_mov_b32_e32 v0, 0 34; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc 35; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 36; GFX11-NEXT: .LBB0_2: ; %bb 37; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 38; GFX11-NEXT: s_waitcnt lgkmcnt(0) 39; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 40; GFX11-NEXT: v_mov_b32_e32 v0, 0 41; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc 42; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 43; GFX11-NEXT: s_endpgm 44entry: 45 %cond = icmp eq i32 %arg0, 0 46 br i1 %cond, label %mid, label %bb 47 48mid: 49 store volatile i32 0, ptr addrspace(1) undef 50 br label %bb 51 52bb: 53 call void @llvm.amdgcn.end.cf.i32(i32 %saved) 54 store volatile i32 0, ptr addrspace(1) undef 55 ret void 56} 57 58declare void @llvm.amdgcn.end.cf.i32(i32 %val) 59