xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir (revision 012a85296b2fc2fe46b0fd90f4c4f7e5d68e5354)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=CI %s
3
4# FIXME: Run with and without unaligned access on
5
6---
7name: test_zextload_constant32bit_s64_s32_align4
8body: |
9  bb.0:
10    liveins: $sgpr0
11
12    ; CI-LABEL: name: test_zextload_constant32bit_s64_s32_align4
13    ; CI: liveins: $sgpr0
14    ; CI-NEXT: {{  $}}
15    ; CI-NEXT: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
16    ; CI-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p6)
17    ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
18    ; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[PTRTOINT]](s32), [[C]](s32)
19    ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), addrspace 6)
20    ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
21    ; CI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
22    %0:_(p6) = COPY $sgpr0
23    %1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), align 4, addrspace 6)
24    $vgpr0_vgpr1 = COPY %1
25...
26
27---
28name: test_zextload_constant32bit_s64_s32_align2
29body: |
30  bb.0:
31    liveins: $sgpr0
32
33    ; CI-LABEL: name: test_zextload_constant32bit_s64_s32_align2
34    ; CI: liveins: $sgpr0
35    ; CI-NEXT: {{  $}}
36    ; CI-NEXT: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
37    ; CI-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p6)
38    ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
39    ; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[PTRTOINT]](s32), [[C]](s32)
40    ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 2, addrspace 6)
41    ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
42    ; CI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
43    %0:_(p6) = COPY $sgpr0
44    %1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), align 2, addrspace 6)
45    $vgpr0_vgpr1 = COPY %1
46...
47
48---
49name: test_zextload_constant32bit_s64_s32_align1
50body: |
51  bb.0:
52    liveins: $sgpr0
53
54    ; CI-LABEL: name: test_zextload_constant32bit_s64_s32_align1
55    ; CI: liveins: $sgpr0
56    ; CI-NEXT: {{  $}}
57    ; CI-NEXT: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
58    ; CI-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p6)
59    ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
60    ; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[PTRTOINT]](s32), [[C]](s32)
61    ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 1, addrspace 6)
62    ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
63    ; CI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
64    %0:_(p6) = COPY $sgpr0
65    %1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), align 1, addrspace 6)
66    $vgpr0_vgpr1 = COPY %1
67...
68
69---
70name: test_zextload_constant32bit_s32_s8_align1
71body: |
72  bb.0:
73    liveins: $sgpr0
74
75    ; CI-LABEL: name: test_zextload_constant32bit_s32_s8_align1
76    ; CI: liveins: $sgpr0
77    ; CI-NEXT: {{  $}}
78    ; CI-NEXT: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
79    ; CI-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p6)
80    ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
81    ; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[PTRTOINT]](s32), [[C]](s32)
82    ; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s8), addrspace 6)
83    ; CI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
84    %0:_(p6) = COPY $sgpr0
85    %1:_(s32) = G_ZEXTLOAD %0 :: (load (s8), align 1, addrspace 6)
86    $vgpr0 = COPY %1
87...
88
89---
90name: test_zextload_constant32bit_s32_s16_align2
91body: |
92  bb.0:
93    liveins: $sgpr0
94
95    ; CI-LABEL: name: test_zextload_constant32bit_s32_s16_align2
96    ; CI: liveins: $sgpr0
97    ; CI-NEXT: {{  $}}
98    ; CI-NEXT: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
99    ; CI-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p6)
100    ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
101    ; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[PTRTOINT]](s32), [[C]](s32)
102    ; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s16), addrspace 6)
103    ; CI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
104    %0:_(p6) = COPY $sgpr0
105    %1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), align 2, addrspace 6)
106    $vgpr0 = COPY %1
107...
108
109---
110name: test_zextload_constant32bit_s32_s16_align1
111body: |
112  bb.0:
113    liveins: $sgpr0
114
115    ; CI-LABEL: name: test_zextload_constant32bit_s32_s16_align1
116    ; CI: liveins: $sgpr0
117    ; CI-NEXT: {{  $}}
118    ; CI-NEXT: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
119    ; CI-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p6)
120    ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
121    ; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[PTRTOINT]](s32), [[C]](s32)
122    ; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s16), align 1, addrspace 6)
123    ; CI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
124    %0:_(p6) = COPY $sgpr0
125    %1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), align 1, addrspace 6)
126    $vgpr0 = COPY %1
127...
128