xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir (revision 8871c3c562690347d75190be758312d1f92a7db4) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefix=SI
3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefix=VI
4---
5name: test_sextload_flat_i32_i8
6body: |
7  bb.0:
8    liveins: $vgpr0_vgpr1
9
10    ; SI-LABEL: name: test_sextload_flat_i32_i8
11    ; SI: liveins: $vgpr0_vgpr1
12    ; SI-NEXT: {{  $}}
13    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
14    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
15    ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
16    ; VI-LABEL: name: test_sextload_flat_i32_i8
17    ; VI: liveins: $vgpr0_vgpr1
18    ; VI-NEXT: {{  $}}
19    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
20    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
21    ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
22    %0:_(p0) = COPY $vgpr0_vgpr1
23    %1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
24    $vgpr0 = COPY %1
25...
26---
27name: test_sextload_flat_i32_i16
28body: |
29  bb.0:
30    liveins: $vgpr0_vgpr1
31
32    ; SI-LABEL: name: test_sextload_flat_i32_i16
33    ; SI: liveins: $vgpr0_vgpr1
34    ; SI-NEXT: {{  $}}
35    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
36    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
37    ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
38    ; VI-LABEL: name: test_sextload_flat_i32_i16
39    ; VI: liveins: $vgpr0_vgpr1
40    ; VI-NEXT: {{  $}}
41    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
42    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
43    ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
44     %0:_(p0) = COPY $vgpr0_vgpr1
45    %1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 0)
46    $vgpr0 = COPY %1
47...
48---
49name: test_sextload_flat_i31_i8
50body: |
51  bb.0:
52    liveins: $vgpr0_vgpr1
53
54    ; SI-LABEL: name: test_sextload_flat_i31_i8
55    ; SI: liveins: $vgpr0_vgpr1
56    ; SI-NEXT: {{  $}}
57    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
58    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
59    ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
60    ; VI-LABEL: name: test_sextload_flat_i31_i8
61    ; VI: liveins: $vgpr0_vgpr1
62    ; VI-NEXT: {{  $}}
63    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
64    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
65    ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
66    %0:_(p0) = COPY $vgpr0_vgpr1
67    %1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
68    %2:_(s32) = G_ANYEXT %1
69    $vgpr0 = COPY %2
70...
71---
72name: test_sextload_flat_i64_i8
73body: |
74  bb.0:
75    liveins: $vgpr0_vgpr1
76
77    ; SI-LABEL: name: test_sextload_flat_i64_i8
78    ; SI: liveins: $vgpr0_vgpr1
79    ; SI-NEXT: {{  $}}
80    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
81    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
82    ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
83    ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
84    ; VI-LABEL: name: test_sextload_flat_i64_i8
85    ; VI: liveins: $vgpr0_vgpr1
86    ; VI-NEXT: {{  $}}
87    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
88    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
89    ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
90    ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
91    %0:_(p0) = COPY $vgpr0_vgpr1
92    %1:_(s64) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
93    $vgpr0_vgpr1 = COPY %1
94...
95---
96name: test_sextload_flat_i64_i16
97body: |
98  bb.0:
99    liveins: $vgpr0_vgpr1
100
101    ; SI-LABEL: name: test_sextload_flat_i64_i16
102    ; SI: liveins: $vgpr0_vgpr1
103    ; SI-NEXT: {{  $}}
104    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
105    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
106    ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
107    ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
108    ; VI-LABEL: name: test_sextload_flat_i64_i16
109    ; VI: liveins: $vgpr0_vgpr1
110    ; VI-NEXT: {{  $}}
111    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
112    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
113    ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
114    ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
115    %0:_(p0) = COPY $vgpr0_vgpr1
116    %1:_(s64) = G_SEXTLOAD %0 :: (load (s16), addrspace 0)
117    $vgpr0_vgpr1 = COPY %1
118...
119---
120name: test_sextload_flat_i64_i32
121body: |
122  bb.0:
123    liveins: $vgpr0_vgpr1
124
125    ; SI-LABEL: name: test_sextload_flat_i64_i32
126    ; SI: liveins: $vgpr0_vgpr1
127    ; SI-NEXT: {{  $}}
128    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
129    ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
130    ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
131    ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
132    ; VI-LABEL: name: test_sextload_flat_i64_i32
133    ; VI: liveins: $vgpr0_vgpr1
134    ; VI-NEXT: {{  $}}
135    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
136    ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
137    ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
138    ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
139    %0:_(p0) = COPY $vgpr0_vgpr1
140    %1:_(s64) = G_SEXTLOAD %0 :: (load (s32), addrspace 0)
141    $vgpr0_vgpr1 = COPY %1
142...
143