1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s 3 4--- 5name: cttz_s32_s32 6 7body: | 8 bb.0: 9 liveins: $vgpr0 10 ; CHECK-LABEL: name: cttz_s32_s32 11 ; CHECK: liveins: $vgpr0 12 ; CHECK-NEXT: {{ $}} 13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 14 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s32) 15 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 16 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]] 17 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32) 18 %0:_(s32) = COPY $vgpr0 19 %1:_(s32) = G_CTTZ %0 20 $vgpr0 = COPY %1 21... 22 23--- 24name: cttz_s32_s64 25 26body: | 27 bb.0: 28 liveins: $vgpr0_vgpr1 29 ; CHECK-LABEL: name: cttz_s32_s64 30 ; CHECK: liveins: $vgpr0_vgpr1 31 ; CHECK-NEXT: {{ $}} 32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 33 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s64) 34 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 35 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]] 36 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32) 37 %0:_(s64) = COPY $vgpr0_vgpr1 38 %1:_(s32) = G_CTTZ %0 39 $vgpr0 = COPY %1 40... 41 42--- 43name: cttz_s64_s64 44 45body: | 46 bb.0: 47 liveins: $vgpr0_vgpr1 48 ; CHECK-LABEL: name: cttz_s64_s64 49 ; CHECK: liveins: $vgpr0_vgpr1 50 ; CHECK-NEXT: {{ $}} 51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 52 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s64) 53 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 54 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]] 55 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UMIN]](s32) 56 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 57 %0:_(s64) = COPY $vgpr0_vgpr1 58 %1:_(s64) = G_CTTZ %0 59 $vgpr0_vgpr1 = COPY %1 60... 61 62--- 63name: cttz_s16_s32 64 65body: | 66 bb.0: 67 liveins: $vgpr0 68 ; CHECK-LABEL: name: cttz_s16_s32 69 ; CHECK: liveins: $vgpr0 70 ; CHECK-NEXT: {{ $}} 71 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 72 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s32) 73 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 74 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]] 75 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32) 76 %0:_(s32) = COPY $vgpr0 77 %1:_(s16) = G_CTTZ %0 78 %2:_(s32) = G_ZEXT %1 79 $vgpr0 = COPY %2 80... 81 82--- 83name: cttz_s16_s16 84 85body: | 86 bb.0: 87 liveins: $vgpr0 88 ; CHECK-LABEL: name: cttz_s16_s16 89 ; CHECK: liveins: $vgpr0 90 ; CHECK-NEXT: {{ $}} 91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 92 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 93 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]] 94 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32) 95 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32) 96 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 97 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] 98 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32) 99 %0:_(s32) = COPY $vgpr0 100 %1:_(s16) = G_TRUNC %0 101 %2:_(s16) = G_CTTZ %1 102 %3:_(s32) = G_ZEXT %2 103 $vgpr0 = COPY %3 104... 105 106--- 107name: cttz_v2s32_v2s32 108 109body: | 110 bb.0: 111 liveins: $vgpr0_vgpr1 112 ; CHECK-LABEL: name: cttz_v2s32_v2s32 113 ; CHECK: liveins: $vgpr0_vgpr1 114 ; CHECK-NEXT: {{ $}} 115 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 116 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 117 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV]](s32) 118 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 119 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]] 120 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s32) 121 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_1]], [[C]] 122 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32) 123 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 124 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 125 %1:_(<2 x s32>) = G_CTTZ %0 126 $vgpr0_vgpr1 = COPY %1 127... 128 129--- 130name: cttz_v2s32_v2s64 131 132body: | 133 bb.0: 134 liveins: $vgpr0_vgpr1_vgpr2_vgpr3 135 ; CHECK-LABEL: name: cttz_v2s32_v2s64 136 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 137 ; CHECK-NEXT: {{ $}} 138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 139 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) 140 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV]](s64) 141 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 142 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]] 143 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s64) 144 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_1]], [[C]] 145 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32) 146 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 147 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 148 %1:_(<2 x s32>) = G_CTTZ %0 149 $vgpr0_vgpr1 = COPY %1 150... 151 152--- 153name: cttz_v2s16_v2s16 154 155body: | 156 bb.0: 157 liveins: $vgpr0 158 ; CHECK-LABEL: name: cttz_v2s16_v2s16 159 ; CHECK: liveins: $vgpr0 160 ; CHECK-NEXT: {{ $}} 161 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 162 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 163 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 164 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 165 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 166 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[BITCAST]], [[C1]] 167 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32) 168 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32) 169 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[C1]] 170 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32) 171 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32) 172 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 173 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] 174 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] 175 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32) 176 ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] 177 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32) 178 ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) 179 %0:_(<2 x s16>) = COPY $vgpr0 180 %1:_(<2 x s16>) = G_CTTZ %0 181 $vgpr0 = COPY %1 182... 183 184--- 185name: cttz_s7_s7 186 187body: | 188 bb.0: 189 liveins: $vgpr0 190 191 ; CHECK-LABEL: name: cttz_s7_s7 192 ; CHECK: liveins: $vgpr0 193 ; CHECK-NEXT: {{ $}} 194 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 195 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 196 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]] 197 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32) 198 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32) 199 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 200 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] 201 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32) 202 %0:_(s32) = COPY $vgpr0 203 %1:_(s7) = G_TRUNC %0 204 %2:_(s7) = G_CTTZ %1 205 %3:_(s32) = G_ZEXT %2 206 $vgpr0 = COPY %3 207... 208 209--- 210name: cttz_s33_s33 211 212body: | 213 bb.0: 214 liveins: $vgpr0_vgpr1 215 216 ; CHECK-LABEL: name: cttz_s33_s33 217 ; CHECK: liveins: $vgpr0_vgpr1 218 ; CHECK-NEXT: {{ $}} 219 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 220 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592 221 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]] 222 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s64) 223 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32) 224 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 225 %0:_(s64) = COPY $vgpr0_vgpr1 226 %1:_(s33) = G_TRUNC %0 227 %2:_(s33) = G_CTTZ %1 228 %3:_(s64) = G_ANYEXT %2 229 $vgpr0_vgpr1 = COPY %3 230... 231