xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir (revision 373c343a77a7afaa07179db1754a52b620dfaf2e) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
3
4---
5name: ctlz_s32_s32
6
7body: |
8  bb.0:
9    liveins: $vgpr0
10    ; CHECK-LABEL: name: ctlz_s32_s32
11    ; CHECK: liveins: $vgpr0
12    ; CHECK-NEXT: {{  $}}
13    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
14    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
15    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
16    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
17    ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)
18    %0:_(s32) = COPY $vgpr0
19    %1:_(s32) = G_CTLZ %0
20    $vgpr0 = COPY %1
21...
22
23---
24name: ctlz_s32_s64
25
26body: |
27  bb.0:
28    liveins: $vgpr0_vgpr1
29    ; CHECK-LABEL: name: ctlz_s32_s64
30    ; CHECK: liveins: $vgpr0_vgpr1
31    ; CHECK-NEXT: {{  $}}
32    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
33    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64)
34    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
35    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
36    ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)
37    %0:_(s64) = COPY $vgpr0_vgpr1
38    %1:_(s32) = G_CTLZ %0
39    $vgpr0 = COPY %1
40...
41
42---
43name: ctlz_s64_s64
44
45body: |
46  bb.0:
47    liveins: $vgpr0_vgpr1
48    ; CHECK-LABEL: name: ctlz_s64_s64
49    ; CHECK: liveins: $vgpr0_vgpr1
50    ; CHECK-NEXT: {{  $}}
51    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
52    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64)
53    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
54    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
55    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UMIN]](s32)
56    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
57    %0:_(s64) = COPY $vgpr0_vgpr1
58    %1:_(s64) = G_CTLZ %0
59    $vgpr0_vgpr1 = COPY %1
60...
61
62---
63name: ctlz_s16_s32
64
65body: |
66  bb.0:
67    liveins: $vgpr0
68    ; CHECK-LABEL: name: ctlz_s16_s32
69    ; CHECK: liveins: $vgpr0
70    ; CHECK-NEXT: {{  $}}
71    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
72    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
73    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
74    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
75    ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)
76    %0:_(s32) = COPY $vgpr0
77    %1:_(s16) = G_CTLZ %0
78    %2:_(s32) = G_ZEXT %1
79    $vgpr0 = COPY %2
80...
81
82---
83name: ctlz_s16_s16
84
85body: |
86  bb.0:
87    liveins: $vgpr0
88    ; CHECK-LABEL: name: ctlz_s16_s16
89    ; CHECK: liveins: $vgpr0
90    ; CHECK-NEXT: {{  $}}
91    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
92    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
93    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
94    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
95    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
96    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
97    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
98    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]
99    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
100    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
101    ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)
102    %0:_(s32) = COPY $vgpr0
103    %1:_(s16) = G_TRUNC %0
104    %2:_(s16) = G_CTLZ %1
105    %3:_(s32) = G_ZEXT %2
106    $vgpr0 = COPY %3
107...
108
109---
110name: ctlz_v2s32_v2s32
111
112body: |
113  bb.0:
114    liveins: $vgpr0_vgpr1
115    ; CHECK-LABEL: name: ctlz_v2s32_v2s32
116    ; CHECK: liveins: $vgpr0_vgpr1
117    ; CHECK-NEXT: {{  $}}
118    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
119    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
120    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV]](s32)
121    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
122    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
123    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s32)
124    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C]]
125    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)
126    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
127    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
128    %1:_(<2 x s32>) = G_CTLZ %0
129    $vgpr0_vgpr1 = COPY %1
130...
131
132---
133name: ctlz_v2s32_v2s64
134
135body: |
136  bb.0:
137    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
138    ; CHECK-LABEL: name: ctlz_v2s32_v2s64
139    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
140    ; CHECK-NEXT: {{  $}}
141    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
142    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
143    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV]](s64)
144    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
145    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
146    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s64)
147    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C]]
148    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)
149    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
150    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
151    %1:_(<2 x s32>) = G_CTLZ %0
152    $vgpr0_vgpr1 = COPY %1
153...
154
155---
156name: ctlz_v2s16_v2s16
157
158body: |
159  bb.0:
160    liveins: $vgpr0
161    ; CHECK-LABEL: name: ctlz_v2s16_v2s16
162    ; CHECK: liveins: $vgpr0
163    ; CHECK-NEXT: {{  $}}
164    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
165    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
166    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
167    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
168    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
169    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
170    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
171    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
172    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C2]]
173    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C]]
174    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
175    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[LSHR]](s32)
176    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C2]]
177    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMIN1]], [[C]]
178    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
179    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
180    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
181    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
182    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
183    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
184    ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
185    %0:_(<2 x s16>) = COPY $vgpr0
186    %1:_(<2 x s16>) = G_CTLZ %0
187    $vgpr0 = COPY %1
188...
189
190---
191name: ctlz_s7_s7
192
193body: |
194  bb.0:
195    liveins: $vgpr0
196
197    ; CHECK-LABEL: name: ctlz_s7_s7
198    ; CHECK: liveins: $vgpr0
199    ; CHECK-NEXT: {{  $}}
200    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
201    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
202    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
203    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
204    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
205    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
206    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
207    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]
208    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
209    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
210    ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)
211    %0:_(s32) = COPY $vgpr0
212    %1:_(s7) = G_TRUNC %0
213    %2:_(s7) = G_CTLZ %1
214    %3:_(s32) = G_ZEXT %2
215    $vgpr0 = COPY %3
216...
217
218---
219name: ctlz_s33_s33
220
221body: |
222  bb.0:
223    liveins: $vgpr0_vgpr1
224
225    ; CHECK-LABEL: name: ctlz_s33_s33
226    ; CHECK: liveins: $vgpr0_vgpr1
227    ; CHECK-NEXT: {{  $}}
228    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
229    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
230    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
231    ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s64)
232    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
233    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
234    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
235    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
236    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UMIN]], [[UV]]
237    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
238    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
239    %0:_(s64) = COPY $vgpr0_vgpr1
240    %1:_(s33) = G_TRUNC %0
241    %2:_(s33) = G_CTLZ %1
242    %3:_(s64) = G_ANYEXT %2
243    $vgpr0_vgpr1 = COPY %3
244...
245
246# ---
247# name: ctlz_v2s7_v2s7
248
249# body: |
250#   bb.0:
251#     liveins: $vgpr0
252#     %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
253#     %1:_(<2 x s7>) = G_TRUNC %0
254#     %2:_(<2 x s7>) = G_CTLZ %1
255#     %3:_(<2 x s32>) = G_ANYEXT %2
256#     $vgpr0_vgpr1 = COPY %3
257# ...
258