xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir (revision 8871c3c562690347d75190be758312d1f92a7db4) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
4
5---
6name: atomicrmw_and_global_i32
7
8body: |
9  bb.0:
10    liveins: $sgpr0_sgpr1, $sgpr2
11    ; CHECK-LABEL: name: atomicrmw_and_global_i32
12    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
13    ; CHECK-NEXT: {{  $}}
14    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
15    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
16    ; CHECK-NEXT: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
17    %0:_(p1) = COPY $sgpr0_sgpr1
18    %1:_(s32) = COPY $sgpr2
19    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 1)
20...
21
22---
23name: atomicrmw_and_local_i32
24
25body: |
26  bb.0:
27    liveins: $sgpr0, $sgpr1
28    ; CHECK-LABEL: name: atomicrmw_and_local_i32
29    ; CHECK: liveins: $sgpr0, $sgpr1
30    ; CHECK-NEXT: {{  $}}
31    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
32    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
33    ; CHECK-NEXT: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
34    %0:_(p3) = COPY $sgpr0
35    %1:_(s32) = COPY $sgpr1
36    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 3)
37...
38
39---
40name: atomicrmw_and_global_i64
41
42body: |
43  bb.0:
44    liveins: $sgpr0_sgpr1, $sgpr2
45    ; CHECK-LABEL: name: atomicrmw_and_global_i64
46    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
47    ; CHECK-NEXT: {{  $}}
48    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
49    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
50    ; CHECK-NEXT: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
51    %0:_(p1) = COPY $sgpr0_sgpr1
52    %1:_(s32) = COPY $sgpr2
53    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 1)
54...
55
56---
57name: atomicrmw_and_local_i64
58
59body: |
60  bb.0:
61    liveins: $sgpr0, $sgpr1
62    ; CHECK-LABEL: name: atomicrmw_and_local_i64
63    ; CHECK: liveins: $sgpr0, $sgpr1
64    ; CHECK-NEXT: {{  $}}
65    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
66    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
67    ; CHECK-NEXT: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
68    %0:_(p3) = COPY $sgpr0
69    %1:_(s32) = COPY $sgpr1
70    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 3)
71...
72