xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -mtriple=amdgcn -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
3
4define i8 @f_i1_1() {
5  ; CHECK-LABEL: name: f_i1_1
6  ; CHECK: bb.1 (%ir-block.0):
7  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(<256 x s8>) = G_IMPLICIT_DEF
8  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
9  ; CHECK-NEXT:   [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<256 x s8>), [[C]](s32)
10  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
11  ; CHECK-NEXT:   $vgpr0 = COPY [[ANYEXT]](s32)
12  ; CHECK-NEXT:   SI_RETURN implicit $vgpr0
13  %E1 = extractelement <256 x i8> undef, i1 true
14  ret i8 %E1
15}
16
17define i8 @f_i8_255() {
18  ; CHECK-LABEL: name: f_i8_255
19  ; CHECK: bb.1 (%ir-block.0):
20  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(<256 x s8>) = G_IMPLICIT_DEF
21  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
22  ; CHECK-NEXT:   [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<256 x s8>), [[C]](s32)
23  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
24  ; CHECK-NEXT:   $vgpr0 = COPY [[ANYEXT]](s32)
25  ; CHECK-NEXT:   SI_RETURN implicit $vgpr0
26  %E1 = extractelement <256 x i8> undef, i8 255
27  ret i8 %E1
28}
29