xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll (revision 35ebd92d3d13925c1a4c61424a7be21cf32dc4c1)
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -global-isel -mtriple=amdgcn -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
3
4define void @prefetch_read(ptr %ptr) {
5  ; CHECK-LABEL: name: prefetch_read
6  ; CHECK: bb.1 (%ir-block.0):
7  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1
8  ; CHECK-NEXT: {{  $}}
9  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
10  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
11  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
12  ; CHECK-NEXT:   G_PREFETCH [[MV]](p0), 0, 0, 0 :: (load unknown-size from %ir.ptr, align 1)
13  ; CHECK-NEXT:   SI_RETURN
14  call void @llvm.prefetch.p0(ptr %ptr, i32 0, i32 0, i32 0)
15  ret void
16}
17
18define void @prefetch_write(ptr %ptr) {
19  ; CHECK-LABEL: name: prefetch_write
20  ; CHECK: bb.1 (%ir-block.0):
21  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1
22  ; CHECK-NEXT: {{  $}}
23  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
24  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
25  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
26  ; CHECK-NEXT:   G_PREFETCH [[MV]](p0), 1, 1, 1 :: (store unknown-size into %ir.ptr, align 1)
27  ; CHECK-NEXT:   SI_RETURN
28  call void @llvm.prefetch.p0(ptr %ptr, i32 1, i32 1, i32 1)
29  ret void
30}
31
32declare void @llvm.prefetch.p0(ptr, i32, i32, i32)
33