xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
4
5# These violate the constant bus restriction pre-gfx10
6
7---
8name: uadde_s32_s1_vsv
9legalized: true
10regBankSelected: true
11
12body: |
13  bb.0:
14    liveins: $sgpr0, $vgpr0
15
16    ; GFX10-LABEL: name: uadde_s32_s1_vsv
17    ; GFX10: liveins: $sgpr0, $vgpr0
18    ; GFX10-NEXT: {{  $}}
19    ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
20    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21    ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
22    ; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
23    ; GFX10-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
24    ; GFX10-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
25    ; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
26    ; GFX10-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
27    ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec
28    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
29    %0:sgpr(s32) = COPY $sgpr0
30    %1:vgpr(s32) = COPY $vgpr0
31    %2:vgpr(s32) = COPY $vgpr2
32    %3:vgpr(s32) = G_CONSTANT i32 0
33    %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
34    %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
35    %7:vgpr(s32) = G_CONSTANT i32 0
36    %8:vgpr(s32) = G_CONSTANT i32 1
37    %9:vgpr(s32) = G_SELECT %6, %7, %8
38    S_ENDPGM 0, implicit %5, implicit %9
39...
40
41---
42name: uadde_s32_s1_vvs
43legalized: true
44regBankSelected: true
45
46body: |
47  bb.0:
48    liveins: $sgpr0, $vgpr0
49
50    ; GFX10-LABEL: name: uadde_s32_s1_vvs
51    ; GFX10: liveins: $sgpr0, $vgpr0
52    ; GFX10-NEXT: {{  $}}
53    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
54    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
55    ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
56    ; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
57    ; GFX10-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
58    ; GFX10-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
59    ; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
60    ; GFX10-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
61    ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec
62    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
63    %0:vgpr(s32) = COPY $vgpr0
64    %1:sgpr(s32) = COPY $sgpr0
65    %2:vgpr(s32) = COPY $vgpr2
66    %3:vgpr(s32) = G_CONSTANT i32 0
67    %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
68    %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
69    %7:vgpr(s32) = G_CONSTANT i32 0
70    %8:vgpr(s32) = G_CONSTANT i32 1
71    %9:vgpr(s32) = G_SELECT %6, %7, %8
72    S_ENDPGM 0, implicit %5, implicit %9
73...
74