xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
3
4---
5name: smed3_s32_vvv
6legalized: true
7regBankSelected: true
8
9body: |
10  bb.0:
11    liveins: $vgpr0, $vgpr1, $vgpr2
12
13    ; GFX6-LABEL: name: smed3_s32_vvv
14    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
15    ; GFX6-NEXT: {{  $}}
16    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
18    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
19    ; GFX6-NEXT: [[V_MED3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
20    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_I32_e64_]]
21    %0:vgpr(s32) = COPY $vgpr0
22    %1:vgpr(s32) = COPY $vgpr1
23    %2:vgpr(s32) = COPY $vgpr2
24    %3:vgpr(s32) = G_SMAX %0, %1
25    %4:vgpr(s32) = G_SMIN %0, %1
26    %5:vgpr(s32) = G_SMAX %4, %2
27    %6:vgpr(s32) = G_SMIN %3, %5
28    S_ENDPGM 0, implicit %6
29...
30
31---
32
33name: smed3_s32_sss
34legalized: true
35regBankSelected: true
36
37body: |
38  bb.0:
39    liveins: $sgpr0, $sgpr1, $sgpr2
40
41    ; GFX6-LABEL: name: smed3_s32_sss
42    ; GFX6: liveins: $sgpr0, $sgpr1, $sgpr2
43    ; GFX6-NEXT: {{  $}}
44    ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
45    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
46    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
47    ; GFX6-NEXT: [[S_MAX_I32_:%[0-9]+]]:sreg_32 = S_MAX_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
48    ; GFX6-NEXT: [[S_MIN_I32_:%[0-9]+]]:sreg_32 = S_MIN_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
49    ; GFX6-NEXT: [[S_MAX_I32_1:%[0-9]+]]:sreg_32 = S_MAX_I32 [[S_MIN_I32_]], [[COPY2]], implicit-def dead $scc
50    ; GFX6-NEXT: [[S_MIN_I32_1:%[0-9]+]]:sreg_32 = S_MIN_I32 [[S_MAX_I32_]], [[S_MAX_I32_1]], implicit-def dead $scc
51    ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_MIN_I32_1]]
52    %0:sgpr(s32) = COPY $sgpr0
53    %1:sgpr(s32) = COPY $sgpr1
54    %2:sgpr(s32) = COPY $sgpr2
55    %3:sgpr(s32) = G_SMAX %0, %1
56    %4:sgpr(s32) = G_SMIN %0, %1
57    %5:sgpr(s32) = G_SMAX %4, %2
58    %6:sgpr(s32) = G_SMIN %3, %5
59    S_ENDPGM 0, implicit %6
60...
61
62---
63name: smed3_s32_vvv_multiuse0
64legalized: true
65regBankSelected: true
66
67body: |
68  bb.0:
69    liveins: $vgpr0, $vgpr1, $vgpr2
70
71    ; GFX6-LABEL: name: smed3_s32_vvv_multiuse0
72    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
73    ; GFX6-NEXT: {{  $}}
74    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
75    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
76    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
77    ; GFX6-NEXT: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
78    ; GFX6-NEXT: [[V_MED3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
79    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_I32_e64_]], implicit [[V_MAX_I32_e64_]]
80    %0:vgpr(s32) = COPY $vgpr0
81    %1:vgpr(s32) = COPY $vgpr1
82    %2:vgpr(s32) = COPY $vgpr2
83    %3:vgpr(s32) = G_SMAX %0, %1
84    %4:vgpr(s32) = G_SMIN %0, %1
85    %5:vgpr(s32) = G_SMAX %4, %2
86    %6:vgpr(s32) = G_SMIN %3, %5
87    S_ENDPGM 0, implicit %6, implicit %3
88...
89
90---
91name: smed3_s32_vvv_multiuse1
92legalized: true
93regBankSelected: true
94
95body: |
96  bb.0:
97    liveins: $vgpr0, $vgpr1, $vgpr2
98
99    ; GFX6-LABEL: name: smed3_s32_vvv_multiuse1
100    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
101    ; GFX6-NEXT: {{  $}}
102    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
103    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
104    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
105    ; GFX6-NEXT: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
106    ; GFX6-NEXT: [[V_MED3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
107    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_I32_e64_]], implicit [[V_MIN_I32_e64_]]
108    %0:vgpr(s32) = COPY $vgpr0
109    %1:vgpr(s32) = COPY $vgpr1
110    %2:vgpr(s32) = COPY $vgpr2
111    %3:vgpr(s32) = G_SMAX %0, %1
112    %4:vgpr(s32) = G_SMIN %0, %1
113    %5:vgpr(s32) = G_SMAX %4, %2
114    %6:vgpr(s32) = G_SMIN %3, %5
115    S_ENDPGM 0, implicit %6, implicit %4
116...
117
118---
119name: smed3_s32_vvv_multiuse2
120legalized: true
121regBankSelected: true
122
123body: |
124  bb.0:
125    liveins: $vgpr0, $vgpr1, $vgpr2
126
127    ; GFX6-LABEL: name: smed3_s32_vvv_multiuse2
128    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
129    ; GFX6-NEXT: {{  $}}
130    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
131    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
132    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
133    ; GFX6-NEXT: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
134    ; GFX6-NEXT: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_MIN_I32_e64_]], [[COPY2]], implicit $exec
135    ; GFX6-NEXT: [[V_MED3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
136    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_I32_e64_]], implicit [[V_MAX_I32_e64_]]
137    %0:vgpr(s32) = COPY $vgpr0
138    %1:vgpr(s32) = COPY $vgpr1
139    %2:vgpr(s32) = COPY $vgpr2
140    %3:vgpr(s32) = G_SMAX %0, %1
141    %4:vgpr(s32) = G_SMIN %0, %1
142    %5:vgpr(s32) = G_SMAX %4, %2
143    %6:vgpr(s32) = G_SMIN %3, %5
144    S_ENDPGM 0, implicit %6, implicit %5
145...
146
147---
148name: smed3_s32_vvv_reuse_bounds
149legalized: true
150regBankSelected: true
151
152body: |
153  bb.0:
154    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
155
156    ; GFX6-LABEL: name: smed3_s32_vvv_reuse_bounds
157    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
158    ; GFX6-NEXT: {{  $}}
159    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
160    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
161    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
162    ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
163    ; GFX6-NEXT: [[V_MED3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
164    ; GFX6-NEXT: [[V_MED3_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MED3_I32_e64 [[COPY]], [[COPY1]], [[COPY3]], implicit $exec
165    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_I32_e64_]], implicit [[V_MED3_I32_e64_1]]
166    %0:vgpr(s32) = COPY $vgpr0
167    %1:vgpr(s32) = COPY $vgpr1
168    %2:vgpr(s32) = COPY $vgpr2
169    %3:vgpr(s32) = COPY $vgpr3
170    %4:vgpr(s32) = G_SMAX %0, %1
171    %5:vgpr(s32) = G_SMIN %0, %1
172    %6:vgpr(s32) = G_SMIN %2, %4
173    %7:vgpr(s32) = G_SMAX %6, %5
174    %8:vgpr(s32) = G_SMIN %3, %4
175    %9:vgpr(s32) = G_SMAX %8, %5
176    S_ENDPGM 0, implicit %7, implicit %9
177...
178