xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
6
7---
8
9name:            add_s32_sgpr_sgpr_sgpr
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13
14body: |
15  bb.0:
16    liveins: $sgpr0, $sgpr1, $sgpr2
17    ; GFX8-LABEL: name: add_s32_sgpr_sgpr_sgpr
18    ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
19    ; GFX8-NEXT: {{  $}}
20    ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
21    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
22    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
23    ; GFX8-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
24    ; GFX8-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def dead $scc
25    ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
26    ;
27    ; GFX9-LABEL: name: add_s32_sgpr_sgpr_sgpr
28    ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
29    ; GFX9-NEXT: {{  $}}
30    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
31    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
32    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
33    ; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
34    ; GFX9-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def dead $scc
35    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
36    %0:sgpr(s32) = COPY $sgpr0
37    %1:sgpr(s32) = COPY $sgpr1
38    %2:sgpr(s32) = COPY $sgpr2
39    %3:sgpr(s32) = G_ADD %0, %1
40    %4:sgpr(s32) = G_ADD %3, %2
41    S_ENDPGM 0, implicit %4
42...
43
44---
45
46name:            add_s32_vgpr_vgpr_vgpr
47legalized:       true
48regBankSelected: true
49tracksRegLiveness: true
50
51body: |
52  bb.0:
53    liveins: $vgpr0, $vgpr1, $vgpr2
54    ; GFX8-LABEL: name: add_s32_vgpr_vgpr_vgpr
55    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
56    ; GFX8-NEXT: {{  $}}
57    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
58    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
59    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
60    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
61    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_ADD_CO_U32_e64_]], [[COPY2]], 0, implicit $exec
62    ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_2]]
63    ;
64    ; GFX9-LABEL: name: add_s32_vgpr_vgpr_vgpr
65    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
66    ; GFX9-NEXT: {{  $}}
67    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
68    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
69    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
70    ; GFX9-NEXT: [[V_ADD3_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
71    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD3_U32_e64_]]
72    %0:vgpr(s32) = COPY $vgpr0
73    %1:vgpr(s32) = COPY $vgpr1
74    %2:vgpr(s32) = COPY $vgpr2
75    %3:vgpr(s32) = G_ADD %0, %1
76    %4:vgpr(s32) = G_ADD %3, %2
77    S_ENDPGM 0, implicit %4
78...
79
80---
81
82name:            add_s32_vgpr_vgpr_vgpr_multi_use
83legalized:       true
84regBankSelected: true
85tracksRegLiveness: true
86
87body: |
88  bb.0:
89    liveins: $vgpr0, $vgpr1, $vgpr2
90    ; GFX8-LABEL: name: add_s32_vgpr_vgpr_vgpr_multi_use
91    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
92    ; GFX8-NEXT: {{  $}}
93    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
94    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
95    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
96    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
97    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_ADD_CO_U32_e64_]], [[COPY2]], 0, implicit $exec
98    ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_2]], implicit [[V_ADD_CO_U32_e64_]]
99    ;
100    ; GFX9-LABEL: name: add_s32_vgpr_vgpr_vgpr_multi_use
101    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
102    ; GFX9-NEXT: {{  $}}
103    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
104    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
105    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
106    ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
107    ; GFX9-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
108    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_]]
109    %0:vgpr(s32) = COPY $vgpr0
110    %1:vgpr(s32) = COPY $vgpr1
111    %2:vgpr(s32) = COPY $vgpr2
112    %3:vgpr(s32) = G_ADD %0, %1
113    %4:vgpr(s32) = G_ADD %3, %2
114    S_ENDPGM 0, implicit %4, implicit %3
115...
116
117---
118
119name:            add_p3_vgpr_vgpr_vgpr
120legalized:       true
121regBankSelected: true
122tracksRegLiveness: true
123
124body: |
125  bb.0:
126    liveins: $vgpr0, $vgpr1, $vgpr2
127
128    ; GFX8-LABEL: name: add_p3_vgpr_vgpr_vgpr
129    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
130    ; GFX8-NEXT: {{  $}}
131    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
132    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
133    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
134    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
135    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_ADD_CO_U32_e64_]], [[COPY2]], 0, implicit $exec
136    ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_2]]
137    ;
138    ; GFX9-LABEL: name: add_p3_vgpr_vgpr_vgpr
139    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
140    ; GFX9-NEXT: {{  $}}
141    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
142    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
143    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
144    ; GFX9-NEXT: [[V_ADD3_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
145    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD3_U32_e64_]]
146    %0:vgpr(p3) = COPY $vgpr0
147    %1:vgpr(s32) = COPY $vgpr1
148    %2:vgpr(s32) = COPY $vgpr2
149    %3:vgpr(p3) = G_PTR_ADD %0, %1
150    %4:vgpr(p3) = G_PTR_ADD %3, %2
151    S_ENDPGM 0, implicit %4
152...
153
154---
155
156name:            add_p5_vgpr_vgpr_vgpr
157legalized:       true
158regBankSelected: true
159tracksRegLiveness: true
160
161body: |
162  bb.0:
163    liveins: $vgpr0, $vgpr1, $vgpr2
164
165    ; GFX8-LABEL: name: add_p5_vgpr_vgpr_vgpr
166    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
167    ; GFX8-NEXT: {{  $}}
168    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
169    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
170    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
171    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
172    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_ADD_CO_U32_e64_]], [[COPY2]], 0, implicit $exec
173    ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_2]]
174    ;
175    ; GFX9-LABEL: name: add_p5_vgpr_vgpr_vgpr
176    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
177    ; GFX9-NEXT: {{  $}}
178    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
179    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
180    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
181    ; GFX9-NEXT: [[V_ADD3_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
182    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD3_U32_e64_]]
183    %0:vgpr(p5) = COPY $vgpr0
184    %1:vgpr(s32) = COPY $vgpr1
185    %2:vgpr(s32) = COPY $vgpr2
186    %3:vgpr(p5) = G_PTR_ADD %0, %1
187    %4:vgpr(p5) = G_PTR_ADD %3, %2
188    S_ENDPGM 0, implicit %4
189...
190
191---
192
193name:            add_p3_s32_vgpr_vgpr_vgpr
194legalized:       true
195regBankSelected: true
196tracksRegLiveness: true
197
198body: |
199  bb.0:
200    liveins: $vgpr0, $vgpr1, $vgpr2
201
202    ; GFX8-LABEL: name: add_p3_s32_vgpr_vgpr_vgpr
203    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
204    ; GFX8-NEXT: {{  $}}
205    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
206    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
207    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
208    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
209    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[V_ADD_CO_U32_e64_]], 0, implicit $exec
210    ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_2]]
211    ;
212    ; GFX9-LABEL: name: add_p3_s32_vgpr_vgpr_vgpr
213    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
214    ; GFX9-NEXT: {{  $}}
215    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
216    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
217    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
218    ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
219    ; GFX9-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[V_ADD_U32_e64_]], 0, implicit $exec
220    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
221    %0:vgpr(s32) = COPY $vgpr0
222    %1:vgpr(s32) = COPY $vgpr1
223    %2:vgpr(p3) = COPY $vgpr2
224    %3:vgpr(s32) = G_ADD %0, %1
225    %4:vgpr(p3) = G_PTR_ADD %2, %3
226    S_ENDPGM 0, implicit %4
227...
228
229---
230
231name:            add_p5_s32_vgpr_vgpr_vgpr
232legalized:       true
233regBankSelected: true
234tracksRegLiveness: true
235
236body: |
237  bb.0:
238    liveins: $vgpr0, $vgpr1, $vgpr2
239
240    ; GFX8-LABEL: name: add_p5_s32_vgpr_vgpr_vgpr
241    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
242    ; GFX8-NEXT: {{  $}}
243    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
244    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
245    ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
246    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
247    ; GFX8-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[V_ADD_CO_U32_e64_]], 0, implicit $exec
248    ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_2]]
249    ;
250    ; GFX9-LABEL: name: add_p5_s32_vgpr_vgpr_vgpr
251    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
252    ; GFX9-NEXT: {{  $}}
253    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
254    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
255    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
256    ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
257    ; GFX9-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[V_ADD_U32_e64_]], 0, implicit $exec
258    ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
259    %0:vgpr(s32) = COPY $vgpr0
260    %1:vgpr(s32) = COPY $vgpr1
261    %2:vgpr(p5) = COPY $vgpr2
262    %3:vgpr(s32) = G_ADD %0, %1
263    %4:vgpr(p5) = G_PTR_ADD %2, %3
264    S_ENDPGM 0, implicit %4
265...
266