xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5
6name:            insert_s512_s32
7legalized:       true
8regBankSelected: true
9
10body: |
11  bb.0:
12    ; CHECK-LABEL: name: insert_s512_s32
13    ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
14    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
15    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0
16    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1
17    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2
18    ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3
19    ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4
20    ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5
21    ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6
22    ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7
23    ; CHECK-NEXT: [[INSERT_SUBREG8:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG7]], [[DEF1]], %subreg.sub8
24    ; CHECK-NEXT: [[INSERT_SUBREG9:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG8]], [[DEF1]], %subreg.sub9
25    ; CHECK-NEXT: [[INSERT_SUBREG10:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG9]], [[DEF1]], %subreg.sub10
26    ; CHECK-NEXT: [[INSERT_SUBREG11:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG10]], [[DEF1]], %subreg.sub11
27    ; CHECK-NEXT: [[INSERT_SUBREG12:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG11]], [[DEF1]], %subreg.sub12
28    ; CHECK-NEXT: [[INSERT_SUBREG13:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG12]], [[DEF1]], %subreg.sub13
29    ; CHECK-NEXT: [[INSERT_SUBREG14:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG13]], [[DEF1]], %subreg.sub14
30    ; CHECK-NEXT: [[INSERT_SUBREG15:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG14]], [[DEF1]], %subreg.sub15
31    ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[INSERT_SUBREG15]]
32    ; CHECK-NEXT: SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
33    %0:sgpr(s512) = G_IMPLICIT_DEF
34    %1:sgpr(s32) = G_IMPLICIT_DEF
35    %2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0
36    %3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32
37    %4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64
38    %5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96
39    %6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128
40    %7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160
41    %8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192
42    %9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224
43    %10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256
44    %11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288
45    %12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320
46    %13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352
47    %14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384
48    %15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416
49    %16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448
50    %17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
51    $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
52    SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
53...
54
55---
56
57name:            insert_v_s64_v_s32_0
58legalized:       true
59regBankSelected: true
60
61body: |
62  bb.0:
63    liveins:  $vgpr0_vgpr1, $vgpr2
64    ; CHECK-LABEL: name: insert_v_s64_v_s32_0
65    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
66    ; CHECK-NEXT: {{  $}}
67    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
68    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
69    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
70    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
71    %0:vgpr(s64) = COPY $vgpr0_vgpr1
72    %1:vgpr(s32) = COPY $vgpr2
73    %2:vgpr(s64) = G_INSERT %0, %1, 0
74    S_ENDPGM 0, implicit %2
75...
76
77---
78
79name:            insert_v_s64_v_s32_32
80legalized:       true
81regBankSelected: true
82
83body: |
84  bb.0:
85    liveins:  $vgpr0_vgpr1, $vgpr2
86    ; CHECK-LABEL: name: insert_v_s64_v_s32_32
87    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
88    ; CHECK-NEXT: {{  $}}
89    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
90    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
91    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
92    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
93    %0:vgpr(s64) = COPY $vgpr0_vgpr1
94    %1:vgpr(s32) = COPY $vgpr2
95    %2:vgpr(s64) = G_INSERT %0, %1, 32
96    S_ENDPGM 0, implicit %2
97...
98
99---
100
101name:            insert_s_s64_s_s32_0
102legalized:       true
103regBankSelected: true
104
105body: |
106  bb.0:
107    liveins:  $sgpr0_sgpr1, $sgpr2
108    ; CHECK-LABEL: name: insert_s_s64_s_s32_0
109    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
110    ; CHECK-NEXT: {{  $}}
111    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
112    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
113    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
114    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
115    %0:sgpr(s64) = COPY $sgpr0_sgpr1
116    %1:sgpr(s32) = COPY $sgpr2
117    %2:sgpr(s64) = G_INSERT %0, %1, 0
118    S_ENDPGM 0, implicit %2
119...
120
121---
122
123name:            insert_s_s64_s_s32_32
124legalized:       true
125regBankSelected: true
126
127body: |
128  bb.0:
129    liveins:  $sgpr0_sgpr1, $sgpr2
130    ; CHECK-LABEL: name: insert_s_s64_s_s32_32
131    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
132    ; CHECK-NEXT: {{  $}}
133    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
134    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
135    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
136    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
137    %0:sgpr(s64) = COPY $sgpr0_sgpr1
138    %1:sgpr(s32) = COPY $sgpr2
139    %2:sgpr(s64) = G_INSERT %0, %1, 32
140    S_ENDPGM 0, implicit %2
141...
142
143---
144
145name:            insert_s_s64_v_s32_32
146legalized:       true
147regBankSelected: true
148
149body: |
150  bb.0:
151    liveins:  $sgpr0_sgpr1, $vgpr0
152    ; CHECK-LABEL: name: insert_s_s64_v_s32_32
153    ; CHECK: liveins: $sgpr0_sgpr1, $vgpr0
154    ; CHECK-NEXT: {{  $}}
155    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
156    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
157    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
158    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
159    %0:sgpr(s64) = COPY $sgpr0_sgpr1
160    %1:vgpr(s32) = COPY $vgpr2
161    %2:vgpr(s64) = G_INSERT %0, %1, 32
162    S_ENDPGM 0, implicit %2
163...
164
165---
166
167name:            insert_v_s64_s_s32_32
168legalized:       true
169regBankSelected: true
170
171body: |
172  bb.0:
173    liveins:  $vgpr0_vgpr1, $sgpr0
174    ; CHECK-LABEL: name: insert_v_s64_s_s32_32
175    ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0
176    ; CHECK-NEXT: {{  $}}
177    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
178    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
179    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
180    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
181    %0:vgpr(s64) = COPY $vgpr0_vgpr1
182    %1:sgpr(s32) = COPY $sgpr0
183    %2:vgpr(s64) = G_INSERT %0, %1, 32
184    S_ENDPGM 0, implicit %2
185...
186
187---
188
189name:            insert_v_s96_v_s64_0
190legalized:       true
191regBankSelected: true
192
193body: |
194  bb.0:
195    liveins:  $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
196    ; CHECK-LABEL: name: insert_v_s96_v_s64_0
197    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
198    ; CHECK-NEXT: {{  $}}
199    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
200    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
201    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
202    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
203    %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
204    %1:vgpr(s64) = COPY $vgpr3_vgpr4
205    %2:vgpr(s96) = G_INSERT %0, %1, 0
206    S_ENDPGM 0, implicit %2
207...
208
209---
210
211name:            insert_v_s96_v_s64_32
212legalized:       true
213regBankSelected: true
214
215body: |
216  bb.0:
217    liveins:  $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
218    ; CHECK-LABEL: name: insert_v_s96_v_s64_32
219    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
220    ; CHECK-NEXT: {{  $}}
221    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
222    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
223    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
224    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
225    %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
226    %1:vgpr(s64) = COPY $vgpr3_vgpr4
227    %2:vgpr(s96) = G_INSERT %0, %1, 32
228    S_ENDPGM 0, implicit %2
229...
230
231---
232
233name:            insert_s_s96_s_s64_0
234legalized:       true
235regBankSelected: true
236
237body: |
238  bb.0:
239    liveins:  $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
240    ; CHECK-LABEL: name: insert_s_s96_s_s64_0
241    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
242    ; CHECK-NEXT: {{  $}}
243    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
244    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
245    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
246    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
247    %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
248    %1:sgpr(s64) = COPY $sgpr4_sgpr5
249    %2:sgpr(s96) = G_INSERT %0, %1, 0
250    S_ENDPGM 0, implicit %2
251...
252
253---
254
255name:            insert_s_s128_s_s64_0
256legalized:       true
257regBankSelected: true
258
259body: |
260  bb.0:
261    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
262    ; CHECK-LABEL: name: insert_s_s128_s_s64_0
263    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
264    ; CHECK-NEXT: {{  $}}
265    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
266    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
267    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
268    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
269    %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
270    %1:sgpr(s64) = COPY $sgpr4_sgpr5
271    %2:sgpr(s128) = G_INSERT %0, %1, 0
272    S_ENDPGM 0, implicit %2
273...
274
275# ---
276
277# name:            insert_s_s128_s_s64_32
278# legalized:       true
279# regBankSelected: true
280
281# body: |
282#   bb.0:
283#     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
284#     %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
285#     %1:sgpr(s64) = COPY $sgpr4_sgpr5
286#     %2:sgpr(s128) = G_INSERT %0, %1, 32
287#     S_ENDPGM 0, implicit %2
288# ...
289
290---
291
292name:            insert_s_s128_s_s64_64
293legalized:       true
294regBankSelected: true
295
296body: |
297  bb.0:
298    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
299    ; CHECK-LABEL: name: insert_s_s128_s_s64_64
300    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
301    ; CHECK-NEXT: {{  $}}
302    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
303    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
304    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
305    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
306    %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
307    %1:sgpr(s64) = COPY $sgpr4_sgpr5
308    %2:sgpr(s128) = G_INSERT %0, %1, 64
309    S_ENDPGM 0, implicit %2
310...
311
312---
313
314name:            insert_s_v256_v_s64_96
315legalized:       true
316regBankSelected: true
317
318body: |
319  bb.0:
320    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
321    ; CHECK-LABEL: name: insert_s_v256_v_s64_96
322    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
323    ; CHECK-NEXT: {{  $}}
324    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
325    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
326    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4
327    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
328    %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
329    %1:vgpr(s64) = COPY $vgpr8_vgpr9
330    %2:vgpr(s256) = G_INSERT %0, %1, 96
331    S_ENDPGM 0, implicit %2
332...
333
334---
335
336name:            insert_s_s256_s_s64_128
337legalized:       true
338regBankSelected: true
339
340body: |
341  bb.0:
342    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
343    ; CHECK-LABEL: name: insert_s_s256_s_s64_128
344    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
345    ; CHECK-NEXT: {{  $}}
346    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
347    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
348    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5
349    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
350    %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
351    %1:sgpr(s64) = COPY $sgpr4_sgpr5
352    %2:sgpr(s256) = G_INSERT %0, %1, 128
353    S_ENDPGM 0, implicit %2
354...
355
356# ---
357
358# name:            insert_s_s256_s_s64_160
359# legalized:       true
360# regBankSelected: true
361
362# body: |
363#   bb.0:
364#     liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
365#     %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
366#     %1:sgpr(s64) = COPY $sgpr4_sgpr5
367#     %2:sgpr(s256) = G_INSERT %0, %1, 160
368#     S_ENDPGM 0, implicit %2
369# ...
370
371---
372
373name:            insert_s_s128_s_s96_0
374legalized:       true
375regBankSelected: true
376
377body: |
378  bb.0:
379    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6
380    ; CHECK-LABEL: name: insert_s_s128_s_s96_0
381    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6
382    ; CHECK-NEXT: {{  $}}
383    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
384    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr4_sgpr5_sgpr6
385    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
386    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
387    %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
388    %1:sgpr(s96) = COPY $sgpr4_sgpr5_sgpr6
389    %2:sgpr(s128) = G_INSERT %0, %1, 0
390    S_ENDPGM 0, implicit %2
391...
392
393---
394
395name:            insert_s_s160_s_s96_0
396legalized:       true
397regBankSelected: true
398
399body: |
400  bb.0:
401    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr8_sgpr9_sgpr10
402    ; CHECK-LABEL: name: insert_s_s160_s_s96_0
403    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr8_sgpr9_sgpr10
404    ; CHECK-NEXT: {{  $}}
405    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
406    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr8_sgpr9_sgpr10
407    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
408    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
409    %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
410    %1:sgpr(s96) = COPY $sgpr8_sgpr9_sgpr10
411    %2:sgpr(s160) = G_INSERT %0, %1, 0
412    S_ENDPGM 0, implicit %2
413...
414
415---
416
417name:            insert_s_s256_s_s128_0
418legalized:       true
419regBankSelected: true
420
421body: |
422  bb.0:
423    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
424
425    ; CHECK-LABEL: name: insert_s_s256_s_s128_0
426    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
427    ; CHECK-NEXT: {{  $}}
428    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
429    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
430    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
431    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
432    %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
433    %1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
434    %2:sgpr(s256) = G_INSERT %0, %1, 0
435    S_ENDPGM 0, implicit %2
436...
437
438---
439
440name:            insert_v_s256_v_s128_32
441legalized:       true
442regBankSelected: true
443
444body: |
445  bb.0:
446    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
447
448    ; CHECK-LABEL: name: insert_v_s256_v_s128_32
449    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
450    ; CHECK-NEXT: {{  $}}
451    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
452    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
453    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4
454    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
455    %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
456    %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
457    %2:vgpr(s256) = G_INSERT %0, %1, 32
458    S_ENDPGM 0, implicit %2
459...
460
461---
462
463name:            insert_v_s256_v_s128_64
464legalized:       true
465regBankSelected: true
466
467body: |
468  bb.0:
469    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
470
471    ; CHECK-LABEL: name: insert_v_s256_v_s128_64
472    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
473    ; CHECK-NEXT: {{  $}}
474    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
475    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
476    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5
477    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
478    %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
479    %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
480    %2:vgpr(s256) = G_INSERT %0, %1, 64
481    S_ENDPGM 0, implicit %2
482...
483
484---
485
486name:            insert_v_s256_v_s128_96
487legalized:       true
488regBankSelected: true
489
490body: |
491  bb.0:
492    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
493
494    ; CHECK-LABEL: name: insert_v_s256_v_s128_96
495    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
496    ; CHECK-NEXT: {{  $}}
497    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
498    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
499    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6
500    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
501    %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
502    %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
503    %2:vgpr(s256) = G_INSERT %0, %1, 96
504    S_ENDPGM 0, implicit %2
505...
506
507---
508
509name:            insert_v_s256_v_s128_128
510legalized:       true
511regBankSelected: true
512
513body: |
514  bb.0:
515    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
516
517    ; CHECK-LABEL: name: insert_v_s256_v_s128_128
518    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
519    ; CHECK-NEXT: {{  $}}
520    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
521    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
522    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7
523    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
524    %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
525    %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
526    %2:vgpr(s256) = G_INSERT %0, %1, 128
527    S_ENDPGM 0, implicit %2
528...
529