xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5
6---
7name: fmul_v2f16_vv
8legalized: true
9regBankSelected: true
10
11body: |
12  bb.0:
13    liveins: $vgpr0, $vgpr1
14
15    ; GFX9-LABEL: name: fmul_v2f16_vv
16    ; GFX9: liveins: $vgpr0, $vgpr1
17    ; GFX9-NEXT: {{  $}}
18    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
20    ; GFX9-NEXT: %2:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
21    ; GFX9-NEXT: S_ENDPGM 0, implicit %2
22    %0:vgpr(<2 x s16>) = COPY $vgpr0
23    %1:vgpr(<2 x s16>) = COPY $vgpr1
24    %2:vgpr(<2 x s16>) = G_FMUL %0, %1
25    S_ENDPGM 0, implicit %2
26...
27
28---
29name: fmul_v2f16_fneg_v_fneg_v
30legalized: true
31regBankSelected: true
32
33body: |
34  bb.0:
35    liveins: $vgpr0, $vgpr1
36
37    ; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v
38    ; GFX9: liveins: $vgpr0, $vgpr1
39    ; GFX9-NEXT: {{  $}}
40    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
41    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
42    ; GFX9-NEXT: %4:vgpr_32 = nofpexcept V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
43    ; GFX9-NEXT: S_ENDPGM 0, implicit %4
44    %0:vgpr(<2 x s16>) = COPY $vgpr0
45    %1:vgpr(<2 x s16>) = COPY $vgpr1
46    %2:vgpr(<2 x s16>) = G_FNEG %0
47    %3:vgpr(<2 x s16>) = G_FNEG %1
48    %4:vgpr(<2 x s16>) = G_FMUL %2, %3
49    S_ENDPGM 0, implicit %4
50...
51
52---
53name: fmul_v2f16_fneg_lo_v_v
54legalized: true
55regBankSelected: true
56
57body: |
58  bb.0:
59    liveins: $vgpr0, $vgpr1, $vgpr2
60
61    ; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v
62    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
63    ; GFX9-NEXT: {{  $}}
64    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
65    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
66    ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
67    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
68    ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
69    ; GFX9-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[V_XOR_B32_e64_]], implicit $exec
70    ; GFX9-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, [[V_AND_B32_e32_]], implicit $exec
71    ; GFX9-NEXT: %7:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[V_LSHL_OR_B32_e64_]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
72    ; GFX9-NEXT: S_ENDPGM 0, implicit %7
73    %0:vgpr(<2 x s16>) = COPY $vgpr0
74    %1:vgpr(s32) = COPY $vgpr1
75    %2:vgpr(s32) = COPY $vgpr2
76    %3:vgpr(s16) = G_TRUNC %1
77    %4:vgpr(s16) = G_FNEG %3
78    %5:vgpr(s32) = G_ANYEXT %4
79    %6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2
80    %7:vgpr(<2 x s16>) = G_FMUL %6, %0
81    S_ENDPGM 0, implicit %7
82...
83