xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5
6---
7name: fminnum_v2f16_vv
8legalized: true
9regBankSelected: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $sgpr1
14
15    ; GFX9-LABEL: name: fminnum_v2f16_vv
16    ; GFX9: liveins: $sgpr0, $sgpr1
17    ; GFX9-NEXT: {{  $}}
18    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
20    ; GFX9-NEXT: %2:vgpr_32 = nofpexcept V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
21    ; GFX9-NEXT: S_ENDPGM 0, implicit %2
22    %0:vgpr(<2 x s16>) = COPY $vgpr0
23    %1:vgpr(<2 x s16>) = COPY $vgpr1
24    %2:vgpr(<2 x s16>) = G_FMINNUM %0, %1
25    S_ENDPGM 0, implicit %2
26...
27