xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
3
4---
5name: ffloor_s32_vv
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $vgpr0
13
14    ; CHECK-LABEL: name: ffloor_s32_vv
15    ; CHECK: liveins: $vgpr0
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
19    ; CHECK-NEXT: $vgpr0 = COPY %1
20    %0:vgpr(s32) = COPY $vgpr0
21    %1:vgpr(s32) = G_FFLOOR %0
22    $vgpr0 = COPY %1
23...
24
25---
26name: ffloor_s32_vs
27legalized: true
28regBankSelected: true
29tracksRegLiveness: true
30
31body: |
32  bb.0:
33    liveins: $sgpr0
34
35    ; CHECK-LABEL: name: ffloor_s32_vs
36    ; CHECK: liveins: $sgpr0
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
39    ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
40    ; CHECK-NEXT: $vgpr0 = COPY %1
41    %0:sgpr(s32) = COPY $sgpr0
42    %1:vgpr(s32) = G_FFLOOR %0
43    $vgpr0 = COPY %1
44...
45
46---
47name: ffloor_fneg_s32_vs
48legalized: true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $sgpr0
55
56    ; CHECK-LABEL: name: ffloor_fneg_s32_vs
57    ; CHECK: liveins: $sgpr0
58    ; CHECK-NEXT: {{  $}}
59    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
60    ; CHECK-NEXT: %2:vgpr_32 = nofpexcept V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
61    ; CHECK-NEXT: $vgpr0 = COPY %2
62    %0:sgpr(s32) = COPY $sgpr0
63    %1:sgpr(s32) = G_FNEG %0
64    %2:vgpr(s32) = G_FFLOOR %1
65    $vgpr0 = COPY %2
66...
67
68---
69name: ffloor_fneg_s32_vv
70legalized: true
71regBankSelected: true
72tracksRegLiveness: true
73
74body: |
75  bb.0:
76    liveins: $vgpr0
77    ; CHECK-LABEL: name: ffloor_fneg_s32_vv
78    ; CHECK: liveins: $vgpr0
79    ; CHECK-NEXT: {{  $}}
80    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
81    ; CHECK-NEXT: %2:vgpr_32 = nofpexcept V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
82    ; CHECK-NEXT: $vgpr0 = COPY %2
83    %0:vgpr(s32) = COPY $vgpr0
84    %1:vgpr(s32) = G_FNEG %0
85    %2:vgpr(s32) = G_FFLOOR %1
86    $vgpr0 = COPY %2
87...
88