xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
3
4---
5
6name:            fadd_s32_vvv
7legalized:       true
8regBankSelected: true
9
10body: |
11  bb.0:
12    liveins: $vgpr0, $vgpr1
13    ; GFX6-LABEL: name: fadd_s32_vvv
14    ; GFX6: liveins: $vgpr0, $vgpr1
15    ; GFX6-NEXT: {{  $}}
16    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
18    ; GFX6-NEXT: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
19    ; GFX6-NEXT: S_ENDPGM 0, implicit %2
20    %0:vgpr(s32) = COPY $vgpr0
21    %1:vgpr(s32) = COPY $vgpr1
22    %2:vgpr(s32) = G_FADD %0, %1
23    S_ENDPGM 0, implicit %2
24
25...
26
27---
28
29name:            fadd_s32_vsv
30legalized:       true
31regBankSelected: true
32
33body: |
34  bb.0:
35    liveins: $vgpr0, $sgpr0
36    ; GFX6-LABEL: name: fadd_s32_vsv
37    ; GFX6: liveins: $vgpr0, $sgpr0
38    ; GFX6-NEXT: {{  $}}
39    ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
40    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
41    ; GFX6-NEXT: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
42    ; GFX6-NEXT: S_ENDPGM 0, implicit %2
43    %0:sgpr(s32) = COPY $sgpr0
44    %1:vgpr(s32) = COPY $vgpr0
45    %2:vgpr(s32) = G_FADD %0, %1
46    S_ENDPGM 0, implicit %2
47
48...
49
50---
51
52name:            fadd_s32_vvs
53legalized:       true
54regBankSelected: true
55
56body: |
57  bb.0:
58    liveins: $vgpr0, $sgpr0
59    ; GFX6-LABEL: name: fadd_s32_vvs
60    ; GFX6: liveins: $vgpr0, $sgpr0
61    ; GFX6-NEXT: {{  $}}
62    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
63    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
64    ; GFX6-NEXT: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
65    ; GFX6-NEXT: S_ENDPGM 0, implicit %2
66    %0:vgpr(s32) = COPY $vgpr0
67    %1:sgpr(s32) = COPY $sgpr0
68    %2:vgpr(s32) = G_FADD %0, %1
69    S_ENDPGM 0, implicit %2
70
71...
72
73---
74
75name:            fadd_s32_vvv_fabs_lhs
76legalized:       true
77regBankSelected: true
78
79body: |
80  bb.0:
81    liveins: $vgpr0, $vgpr1
82    ; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
83    ; GFX6: liveins: $vgpr0, $vgpr1
84    ; GFX6-NEXT: {{  $}}
85    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
86    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
87    ; GFX6-NEXT: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
88    ; GFX6-NEXT: S_ENDPGM 0, implicit %3
89    %0:vgpr(s32) = COPY $vgpr0
90    %1:vgpr(s32) = COPY $vgpr1
91    %2:vgpr(s32) = G_FABS %0
92    %3:vgpr(s32) = G_FADD %2, %1
93    S_ENDPGM 0, implicit %3
94
95...
96
97---
98
99name:            fadd_s32_vvv_fabs_rhs
100legalized:       true
101regBankSelected: true
102
103body: |
104  bb.0:
105    liveins: $vgpr0, $vgpr1
106    ; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
107    ; GFX6: liveins: $vgpr0, $vgpr1
108    ; GFX6-NEXT: {{  $}}
109    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
110    ; GFX6-NEXT: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
111    ; GFX6-NEXT: S_ENDPGM 0, implicit %3
112    %0:vgpr(s32) = COPY $vgpr0
113    %1:vgpr(s32) = COPY $vgpr1
114    %2:vgpr(s32) = G_FABS %1
115    %3:vgpr(s32) = G_FADD %1, %2
116    S_ENDPGM 0, implicit %3
117
118...
119
120---
121
122name:            fadd_s32_vvv_fneg_fabs_lhs
123legalized:       true
124regBankSelected: true
125
126body: |
127  bb.0:
128    liveins: $vgpr0, $vgpr1
129    ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
130    ; GFX6: liveins: $vgpr0, $vgpr1
131    ; GFX6-NEXT: {{  $}}
132    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
133    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
134    ; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
135    ; GFX6-NEXT: S_ENDPGM 0, implicit %4
136    %0:vgpr(s32) = COPY $vgpr0
137    %1:vgpr(s32) = COPY $vgpr1
138    %2:vgpr(s32) = G_FABS %0
139    %3:vgpr(s32) = G_FNEG %2
140    %4:vgpr(s32) = G_FADD %3, %1
141    S_ENDPGM 0, implicit %4
142
143...
144
145---
146
147name:            fadd_s32_vvv_fneg_fabs_rhs
148legalized:       true
149regBankSelected: true
150
151body: |
152  bb.0:
153    liveins: $vgpr0, $vgpr1
154    ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
155    ; GFX6: liveins: $vgpr0, $vgpr1
156    ; GFX6-NEXT: {{  $}}
157    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
158    ; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec
159    ; GFX6-NEXT: S_ENDPGM 0, implicit %4
160    %0:vgpr(s32) = COPY $vgpr0
161    %1:vgpr(s32) = COPY $vgpr1
162    %2:vgpr(s32) = G_FABS %1
163    %3:vgpr(s32) = G_FNEG %2
164    %4:vgpr(s32) = G_FADD %1, %3
165    S_ENDPGM 0, implicit %4
166
167...
168
169# Need to look through reg bank copy to find source modifiers
170---
171
172name:            fadd_s32_fneg_copy_sgpr
173legalized:       true
174regBankSelected: true
175
176body: |
177  bb.0:
178    liveins: $vgpr0, $sgpr0
179    ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
180    ; GFX6: liveins: $vgpr0, $sgpr0
181    ; GFX6-NEXT: {{  $}}
182    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
183    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
184    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
185    ; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
186    ; GFX6-NEXT: S_ENDPGM 0, implicit %4
187    %0:vgpr(s32) = COPY $vgpr0
188    %1:sgpr(s32) = COPY $sgpr0
189    %2:sgpr(s32) = G_FNEG %1
190    %3:vgpr(s32) = COPY %2
191    %4:vgpr(s32) = G_FADD %0, %3
192    S_ENDPGM 0, implicit %4
193
194...
195
196# Need to look through copy in between fneg and fabs
197
198---
199
200name:            fadd_s32_copy_fneg_copy_fabs
201legalized:       true
202regBankSelected: true
203
204body: |
205  bb.0:
206    liveins: $vgpr0, $sgpr0
207    ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
208    ; GFX6: liveins: $vgpr0, $sgpr0
209    ; GFX6-NEXT: {{  $}}
210    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
211    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
212    ; GFX6-NEXT: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec
213    ; GFX6-NEXT: S_ENDPGM 0, implicit %6
214    %0:vgpr(s32) = COPY $vgpr0
215    %1:sgpr(s32) = COPY $sgpr0
216    %2:sgpr(s32) = G_FABS %1
217    %3:sgpr(s32) = COPY %2
218    %4:sgpr(s32) = G_FNEG %3
219    %5:sgpr(s32) = COPY %4
220    %6:vgpr(s32) = G_FADD %0, %5
221    S_ENDPGM 0, implicit %6
222
223...
224
225# The source modifier lookup searches through SGPR->VGPR copies. Make
226# sure we don't violate the constant bus restriction when we look at
227# the source.
228
229---
230
231name:            fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
232legalized:       true
233regBankSelected: true
234
235body: |
236  bb.0:
237    liveins: $sgpr0, $sgpr1
238    ; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
239    ; GFX6: liveins: $sgpr0, $sgpr1
240    ; GFX6-NEXT: {{  $}}
241    ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
242    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
243    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
244    ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
245    ; GFX6-NEXT: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec
246    ; GFX6-NEXT: S_ENDPGM 0, implicit %6
247    %0:sgpr(s32) = COPY $sgpr0
248    %1:sgpr(s32) = COPY $sgpr1
249    %2:sgpr(s32) = G_FABS %0
250    %3:sgpr(s32) = G_FABS %1
251    %4:vgpr(s32) = COPY %2
252    %5:vgpr(s32) = COPY %3
253    %6:vgpr(s32) = G_FADD %4, %5
254    S_ENDPGM 0, implicit %6
255
256...
257
258---
259
260name:            fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
261legalized:       true
262regBankSelected: true
263
264body: |
265  bb.0:
266    liveins: $sgpr0, $sgpr1
267    ; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
268    ; GFX6: liveins: $sgpr0, $sgpr1
269    ; GFX6-NEXT: {{  $}}
270    ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
271    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
272    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
273    ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
274    ; GFX6-NEXT: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec
275    ; GFX6-NEXT: S_ENDPGM 0, implicit %6
276    %0:sgpr(s32) = COPY $sgpr0
277    %1:sgpr(s32) = COPY $sgpr1
278    %2:sgpr(s32) = G_FNEG %0
279    %3:sgpr(s32) = G_FNEG %1
280    %4:vgpr(s32) = COPY %2
281    %5:vgpr(s32) = COPY %3
282    %6:vgpr(s32) = G_FADD %4, %5
283    S_ENDPGM 0, implicit %6
284
285...
286
287---
288
289name:            fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
290legalized:       true
291regBankSelected: true
292
293body: |
294  bb.0:
295    liveins: $sgpr0, $sgpr1
296    ; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
297    ; GFX6: liveins: $sgpr0, $sgpr1
298    ; GFX6-NEXT: {{  $}}
299    ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
300    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
301    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
302    ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
303    ; GFX6-NEXT: %8:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec
304    ; GFX6-NEXT: S_ENDPGM 0, implicit %8
305    %0:sgpr(s32) = COPY $sgpr0
306    %1:sgpr(s32) = COPY $sgpr1
307    %2:sgpr(s32) = G_FABS %0
308    %3:sgpr(s32) = G_FABS %1
309    %4:sgpr(s32) = G_FNEG %2
310    %5:sgpr(s32) = G_FNEG %3
311    %6:vgpr(s32) = COPY %4
312    %7:vgpr(s32) = COPY %5
313    %8:vgpr(s32) = G_FADD %6, %7
314    S_ENDPGM 0, implicit %8
315
316...
317