1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s 3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI %s 4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s 5# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s 6# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s 7 8--- 9name: fabs_s32_ss 10legalized: true 11regBankSelected: true 12tracksRegLiveness: true 13 14body: | 15 bb.0: 16 liveins: $sgpr0 17 ; SI-LABEL: name: fabs_s32_ss 18 ; SI: liveins: $sgpr0 19 ; SI-NEXT: {{ $}} 20 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 21 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 22 ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 23 ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 24 ; 25 ; VI-LABEL: name: fabs_s32_ss 26 ; VI: liveins: $sgpr0 27 ; VI-NEXT: {{ $}} 28 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 29 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 30 ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 31 ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 32 ; 33 ; GFX9-LABEL: name: fabs_s32_ss 34 ; GFX9: liveins: $sgpr0 35 ; GFX9-NEXT: {{ $}} 36 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 37 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 38 ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 39 ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 40 ; 41 ; GFX10-LABEL: name: fabs_s32_ss 42 ; GFX10: liveins: $sgpr0 43 ; GFX10-NEXT: {{ $}} 44 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 45 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 46 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 47 ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 48 %0:sgpr(s32) = COPY $sgpr0 49 %1:sgpr(s32) = G_FABS %0 50 $sgpr0 = COPY %1 51... 52 53--- 54name: fabs_s32_vv 55legalized: true 56regBankSelected: true 57tracksRegLiveness: true 58 59body: | 60 bb.0: 61 liveins: $vgpr0 62 ; SI-LABEL: name: fabs_s32_vv 63 ; SI: liveins: $vgpr0 64 ; SI-NEXT: {{ $}} 65 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 66 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 67 ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 68 ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 69 ; 70 ; VI-LABEL: name: fabs_s32_vv 71 ; VI: liveins: $vgpr0 72 ; VI-NEXT: {{ $}} 73 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 74 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 75 ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 76 ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 77 ; 78 ; GFX9-LABEL: name: fabs_s32_vv 79 ; GFX9: liveins: $vgpr0 80 ; GFX9-NEXT: {{ $}} 81 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 82 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 83 ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 84 ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 85 ; 86 ; GFX10-LABEL: name: fabs_s32_vv 87 ; GFX10: liveins: $vgpr0 88 ; GFX10-NEXT: {{ $}} 89 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 90 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 91 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 92 ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 93 %0:vgpr(s32) = COPY $vgpr0 94 %1:vgpr(s32) = G_FABS %0 95 $vgpr0 = COPY %1 96... 97 98--- 99name: fabs_s32_vs 100legalized: true 101regBankSelected: true 102tracksRegLiveness: true 103 104body: | 105 bb.0: 106 liveins: $sgpr0 107 ; SI-LABEL: name: fabs_s32_vs 108 ; SI: liveins: $sgpr0 109 ; SI-NEXT: {{ $}} 110 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 111 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 112 ; SI-NEXT: $vgpr0 = COPY [[FABS]](s32) 113 ; 114 ; VI-LABEL: name: fabs_s32_vs 115 ; VI: liveins: $sgpr0 116 ; VI-NEXT: {{ $}} 117 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 118 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 119 ; VI-NEXT: $vgpr0 = COPY [[FABS]](s32) 120 ; 121 ; GFX9-LABEL: name: fabs_s32_vs 122 ; GFX9: liveins: $sgpr0 123 ; GFX9-NEXT: {{ $}} 124 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 125 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 126 ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](s32) 127 ; 128 ; GFX10-LABEL: name: fabs_s32_vs 129 ; GFX10: liveins: $sgpr0 130 ; GFX10-NEXT: {{ $}} 131 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 132 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]] 133 ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](s32) 134 %0:sgpr(s32) = COPY $sgpr0 135 %1:vgpr(s32) = G_FABS %0 136 $vgpr0 = COPY %1 137... 138 139--- 140name: fabs_v2s16_ss 141legalized: true 142regBankSelected: true 143tracksRegLiveness: true 144 145body: | 146 bb.0: 147 liveins: $sgpr0_sgpr1 148 ; SI-LABEL: name: fabs_v2s16_ss 149 ; SI: liveins: $sgpr0_sgpr1 150 ; SI-NEXT: {{ $}} 151 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 152 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 153 ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 154 ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 155 ; 156 ; VI-LABEL: name: fabs_v2s16_ss 157 ; VI: liveins: $sgpr0_sgpr1 158 ; VI-NEXT: {{ $}} 159 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 160 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 161 ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 162 ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 163 ; 164 ; GFX9-LABEL: name: fabs_v2s16_ss 165 ; GFX9: liveins: $sgpr0_sgpr1 166 ; GFX9-NEXT: {{ $}} 167 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 168 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 169 ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 170 ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 171 ; 172 ; GFX10-LABEL: name: fabs_v2s16_ss 173 ; GFX10: liveins: $sgpr0_sgpr1 174 ; GFX10-NEXT: {{ $}} 175 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 176 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 177 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 178 ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 179 %0:sgpr(<2 x s16>) = COPY $sgpr0 180 %1:sgpr(<2 x s16>) = G_FABS %0 181 $sgpr0 = COPY %1 182... 183 184--- 185name: fabs_s16_ss 186legalized: true 187regBankSelected: true 188tracksRegLiveness: true 189 190body: | 191 bb.0: 192 liveins: $sgpr0 193 ; SI-LABEL: name: fabs_s16_ss 194 ; SI: liveins: $sgpr0 195 ; SI-NEXT: {{ $}} 196 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 197 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 198 ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 199 ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 200 ; 201 ; VI-LABEL: name: fabs_s16_ss 202 ; VI: liveins: $sgpr0 203 ; VI-NEXT: {{ $}} 204 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 205 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 206 ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 207 ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 208 ; 209 ; GFX9-LABEL: name: fabs_s16_ss 210 ; GFX9: liveins: $sgpr0 211 ; GFX9-NEXT: {{ $}} 212 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 213 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 214 ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 215 ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 216 ; 217 ; GFX10-LABEL: name: fabs_s16_ss 218 ; GFX10: liveins: $sgpr0 219 ; GFX10-NEXT: {{ $}} 220 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 221 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 222 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 223 ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 224 %0:sgpr(s32) = COPY $sgpr0 225 %1:sgpr(s16) = G_TRUNC %0 226 %2:sgpr(s16) = G_FABS %1 227 %3:sgpr(s32) = G_ANYEXT %2 228 $sgpr0 = COPY %3 229... 230 231--- 232name: fabs_s16_vv 233legalized: true 234regBankSelected: true 235tracksRegLiveness: true 236 237body: | 238 bb.0: 239 liveins: $vgpr0 240 ; SI-LABEL: name: fabs_s16_vv 241 ; SI: liveins: $vgpr0 242 ; SI-NEXT: {{ $}} 243 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 244 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 245 ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 246 ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 247 ; 248 ; VI-LABEL: name: fabs_s16_vv 249 ; VI: liveins: $vgpr0 250 ; VI-NEXT: {{ $}} 251 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 252 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 253 ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 254 ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 255 ; 256 ; GFX9-LABEL: name: fabs_s16_vv 257 ; GFX9: liveins: $vgpr0 258 ; GFX9-NEXT: {{ $}} 259 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 260 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 261 ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 262 ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 263 ; 264 ; GFX10-LABEL: name: fabs_s16_vv 265 ; GFX10: liveins: $vgpr0 266 ; GFX10-NEXT: {{ $}} 267 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 268 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767 269 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 270 ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 271 %0:vgpr(s32) = COPY $vgpr0 272 %1:vgpr(s16) = G_TRUNC %0 273 %2:vgpr(s16) = G_FABS %1 274 %3:vgpr(s32) = G_ANYEXT %2 275 $vgpr0 = COPY %3 276... 277 278--- 279name: fabs_s16_vs 280legalized: true 281regBankSelected: true 282tracksRegLiveness: true 283 284body: | 285 bb.0: 286 liveins: $sgpr0 287 288 ; SI-LABEL: name: fabs_s16_vs 289 ; SI: liveins: $sgpr0 290 ; SI-NEXT: {{ $}} 291 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 292 ; SI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 293 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]] 294 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16) 295 ; SI-NEXT: $vgpr0 = COPY [[COPY1]](s32) 296 ; 297 ; VI-LABEL: name: fabs_s16_vs 298 ; VI: liveins: $sgpr0 299 ; VI-NEXT: {{ $}} 300 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 301 ; VI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 302 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]] 303 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16) 304 ; VI-NEXT: $vgpr0 = COPY [[COPY1]](s32) 305 ; 306 ; GFX9-LABEL: name: fabs_s16_vs 307 ; GFX9: liveins: $sgpr0 308 ; GFX9-NEXT: {{ $}} 309 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 310 ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 311 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]] 312 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16) 313 ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32) 314 ; 315 ; GFX10-LABEL: name: fabs_s16_vs 316 ; GFX10: liveins: $sgpr0 317 ; GFX10-NEXT: {{ $}} 318 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 319 ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 320 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]] 321 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16) 322 ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]](s32) 323 %0:sgpr(s32) = COPY $sgpr0 324 %1:sgpr(s16) = G_TRUNC %0 325 %2:vgpr(s16) = G_FABS %1 326 %3:vgpr(s32) = G_ANYEXT %2 327 $vgpr0 = COPY %3 328... 329 330--- 331name: fabs_v2s16_vv 332legalized: true 333regBankSelected: true 334tracksRegLiveness: true 335 336body: | 337 bb.0: 338 liveins: $vgpr0 339 ; SI-LABEL: name: fabs_v2s16_vv 340 ; SI: liveins: $vgpr0 341 ; SI-NEXT: {{ $}} 342 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 343 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 344 ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 345 ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 346 ; 347 ; VI-LABEL: name: fabs_v2s16_vv 348 ; VI: liveins: $vgpr0 349 ; VI-NEXT: {{ $}} 350 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 351 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 352 ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 353 ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 354 ; 355 ; GFX9-LABEL: name: fabs_v2s16_vv 356 ; GFX9: liveins: $vgpr0 357 ; GFX9-NEXT: {{ $}} 358 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 359 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 360 ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 361 ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 362 ; 363 ; GFX10-LABEL: name: fabs_v2s16_vv 364 ; GFX10: liveins: $vgpr0 365 ; GFX10-NEXT: {{ $}} 366 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 367 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879 368 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 369 ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 370 %0:vgpr(<2 x s16>) = COPY $vgpr0 371 %1:vgpr(<2 x s16>) = G_FABS %0 372 $vgpr0 = COPY %1 373... 374 375--- 376name: fabs_v2s16_vs 377legalized: true 378regBankSelected: true 379tracksRegLiveness: true 380 381body: | 382 bb.0: 383 liveins: $sgpr0 384 ; SI-LABEL: name: fabs_v2s16_vs 385 ; SI: liveins: $sgpr0 386 ; SI-NEXT: {{ $}} 387 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 388 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 389 ; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>) 390 ; 391 ; VI-LABEL: name: fabs_v2s16_vs 392 ; VI: liveins: $sgpr0 393 ; VI-NEXT: {{ $}} 394 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 395 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 396 ; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>) 397 ; 398 ; GFX9-LABEL: name: fabs_v2s16_vs 399 ; GFX9: liveins: $sgpr0 400 ; GFX9-NEXT: {{ $}} 401 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 402 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 403 ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>) 404 ; 405 ; GFX10-LABEL: name: fabs_v2s16_vs 406 ; GFX10: liveins: $sgpr0 407 ; GFX10-NEXT: {{ $}} 408 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 409 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]] 410 ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>) 411 %0:sgpr(<2 x s16>) = COPY $sgpr0 412 %1:vgpr(<2 x s16>) = G_FABS %0 413 $vgpr0 = COPY %1 414... 415 416--- 417name: fabs_s64_ss 418legalized: true 419regBankSelected: true 420tracksRegLiveness: true 421 422body: | 423 bb.0: 424 liveins: $sgpr0_sgpr1 425 ; SI-LABEL: name: fabs_s64_ss 426 ; SI: liveins: $sgpr0_sgpr1 427 ; SI-NEXT: {{ $}} 428 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 429 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 430 ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 431 ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 432 ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 433 ; SI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 434 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 435 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 436 ; 437 ; VI-LABEL: name: fabs_s64_ss 438 ; VI: liveins: $sgpr0_sgpr1 439 ; VI-NEXT: {{ $}} 440 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 441 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 442 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 443 ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 444 ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 445 ; VI-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 446 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 447 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 448 ; 449 ; GFX9-LABEL: name: fabs_s64_ss 450 ; GFX9: liveins: $sgpr0_sgpr1 451 ; GFX9-NEXT: {{ $}} 452 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 453 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 454 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 455 ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 456 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 457 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 458 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 459 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 460 ; 461 ; GFX10-LABEL: name: fabs_s64_ss 462 ; GFX10: liveins: $sgpr0_sgpr1 463 ; GFX10-NEXT: {{ $}} 464 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 465 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 466 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1 467 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 468 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 469 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0 470 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 471 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 472 %0:sgpr(s64) = COPY $sgpr0_sgpr1 473 %1:sgpr(s64) = G_FABS %0 474 S_ENDPGM 0, implicit %1 475... 476 477--- 478name: fabs_s64_vv 479legalized: true 480regBankSelected: true 481tracksRegLiveness: true 482 483body: | 484 bb.0: 485 liveins: $vgpr0_vgpr1 486 ; SI-LABEL: name: fabs_s64_vv 487 ; SI: liveins: $vgpr0_vgpr1 488 ; SI-NEXT: {{ $}} 489 ; SI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 490 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 491 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 492 ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 493 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 494 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 495 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 496 ; 497 ; VI-LABEL: name: fabs_s64_vv 498 ; VI: liveins: $vgpr0_vgpr1 499 ; VI-NEXT: {{ $}} 500 ; VI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 501 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 502 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 503 ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 504 ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 505 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 506 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 507 ; 508 ; GFX9-LABEL: name: fabs_s64_vv 509 ; GFX9: liveins: $vgpr0_vgpr1 510 ; GFX9-NEXT: {{ $}} 511 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 512 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 513 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 514 ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 515 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 516 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 517 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 518 ; 519 ; GFX10-LABEL: name: fabs_s64_vv 520 ; GFX10: liveins: $vgpr0_vgpr1 521 ; GFX10-NEXT: {{ $}} 522 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 523 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 524 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 525 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec 526 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 527 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 528 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 529 %0:vgpr(s64) = COPY $vgpr0_vgpr1 530 %1:vgpr(s64) = G_FABS %0 531 S_ENDPGM 0, implicit %1 532... 533 534--- 535name: fabs_s64_vs 536legalized: true 537regBankSelected: true 538tracksRegLiveness: true 539 540body: | 541 bb.0: 542 liveins: $sgpr0_sgpr1 543 ; SI-LABEL: name: fabs_s64_vs 544 ; SI: liveins: $sgpr0_sgpr1 545 ; SI-NEXT: {{ $}} 546 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 547 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]] 548 ; SI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64) 549 ; 550 ; VI-LABEL: name: fabs_s64_vs 551 ; VI: liveins: $sgpr0_sgpr1 552 ; VI-NEXT: {{ $}} 553 ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 554 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]] 555 ; VI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64) 556 ; 557 ; GFX9-LABEL: name: fabs_s64_vs 558 ; GFX9: liveins: $sgpr0_sgpr1 559 ; GFX9-NEXT: {{ $}} 560 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 561 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]] 562 ; GFX9-NEXT: S_ENDPGM 0, implicit [[FABS]](s64) 563 ; 564 ; GFX10-LABEL: name: fabs_s64_vs 565 ; GFX10: liveins: $sgpr0_sgpr1 566 ; GFX10-NEXT: {{ $}} 567 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 568 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]] 569 ; GFX10-NEXT: S_ENDPGM 0, implicit [[FABS]](s64) 570 %0:sgpr(s64) = COPY $sgpr0_sgpr1 571 %1:vgpr(s64) = G_FABS %0 572 S_ENDPGM 0, implicit %1 573... 574 575# Make sure the source register is constrained 576--- 577name: fabs_s64_vv_no_src_constraint 578legalized: true 579regBankSelected: true 580tracksRegLiveness: true 581 582body: | 583 bb.0: 584 liveins: $vgpr0_vgpr1 585 ; SI-LABEL: name: fabs_s64_vv_no_src_constraint 586 ; SI: liveins: $vgpr0_vgpr1 587 ; SI-NEXT: {{ $}} 588 ; SI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF 589 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 590 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 591 ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 592 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 593 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 594 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 595 ; 596 ; VI-LABEL: name: fabs_s64_vv_no_src_constraint 597 ; VI: liveins: $vgpr0_vgpr1 598 ; VI-NEXT: {{ $}} 599 ; VI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF 600 ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 601 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 602 ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 603 ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 604 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 605 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 606 ; 607 ; GFX9-LABEL: name: fabs_s64_vv_no_src_constraint 608 ; GFX9: liveins: $vgpr0_vgpr1 609 ; GFX9-NEXT: {{ $}} 610 ; GFX9-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF 611 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 612 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 613 ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 614 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 615 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 616 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 617 ; 618 ; GFX10-LABEL: name: fabs_s64_vv_no_src_constraint 619 ; GFX10: liveins: $vgpr0_vgpr1 620 ; GFX10-NEXT: {{ $}} 621 ; GFX10-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF 622 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 623 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 624 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 625 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 626 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1 627 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 628 %0:vgpr(s64) = IMPLICIT_DEF 629 %1:vgpr(s64) = G_FABS %0:vgpr(s64) 630 S_ENDPGM 0, implicit %1 631... 632 633--- 634name: fabs_s64_ss_no_src_constraint 635legalized: true 636regBankSelected: true 637tracksRegLiveness: true 638 639body: | 640 bb.0: 641 liveins: $sgpr0_sgpr1 642 ; SI-LABEL: name: fabs_s64_ss_no_src_constraint 643 ; SI: liveins: $sgpr0_sgpr1 644 ; SI-NEXT: {{ $}} 645 ; SI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF 646 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 647 ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1 648 ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 649 ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 650 ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0 651 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 652 ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 653 ; 654 ; VI-LABEL: name: fabs_s64_ss_no_src_constraint 655 ; VI: liveins: $sgpr0_sgpr1 656 ; VI-NEXT: {{ $}} 657 ; VI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF 658 ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 659 ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1 660 ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 661 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 662 ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0 663 ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 664 ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 665 ; 666 ; GFX9-LABEL: name: fabs_s64_ss_no_src_constraint 667 ; GFX9: liveins: $sgpr0_sgpr1 668 ; GFX9-NEXT: {{ $}} 669 ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF 670 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 671 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1 672 ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 673 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 674 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0 675 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 676 ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 677 ; 678 ; GFX10-LABEL: name: fabs_s64_ss_no_src_constraint 679 ; GFX10: liveins: $sgpr0_sgpr1 680 ; GFX10-NEXT: {{ $}} 681 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF 682 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647 683 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1 684 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 685 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]] 686 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0 687 ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 688 ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 689 %0:sgpr(s64) = IMPLICIT_DEF 690 %1:sgpr(s64) = G_FABS %0:sgpr(s64) 691 S_ENDPGM 0, implicit %1 692... 693