xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: ctlz_zero_undef_s32_ss
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0
13
14    ; CHECK-LABEL: name: ctlz_zero_undef_s32_ss
15    ; CHECK: liveins: $sgpr0
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; CHECK-NEXT: [[S_FLBIT_I32_B32_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B32 [[COPY]]
19    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_B32_]]
20    %0:sgpr(s32) = COPY $sgpr0
21    %1:sgpr(s32) = G_CTLZ_ZERO_UNDEF %0
22    S_ENDPGM 0, implicit %1
23...
24
25---
26name: ctlz_zero_undef_s32_vs
27legalized: true
28regBankSelected: true
29tracksRegLiveness: true
30
31body: |
32  bb.0:
33    liveins: $sgpr0
34
35    ; CHECK-LABEL: name: ctlz_zero_undef_s32_vs
36    ; CHECK: liveins: $sgpr0
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
39    ; CHECK-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
40    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
41    %0:sgpr(s32) = COPY $sgpr0
42    %1:vgpr(s32) = G_CTLZ_ZERO_UNDEF %0
43    S_ENDPGM 0, implicit %1
44...
45
46---
47name: ctlz_zero_undef_s32_vv
48legalized: true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $vgpr0
55
56    ; CHECK-LABEL: name: ctlz_zero_undef_s32_vv
57    ; CHECK: liveins: $vgpr0
58    ; CHECK-NEXT: {{  $}}
59    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
60    ; CHECK-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
61    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
62    %0:vgpr(s32) = COPY $vgpr0
63    %1:vgpr(s32) = G_CTLZ_ZERO_UNDEF %0
64    S_ENDPGM 0, implicit %1
65...
66
67---
68name: ctlz_zero_undef_s64_ss
69legalized: true
70regBankSelected: true
71tracksRegLiveness: true
72
73body: |
74  bb.0:
75    liveins: $sgpr0_sgpr1
76
77    ; CHECK-LABEL: name: ctlz_zero_undef_s64_ss
78    ; CHECK: liveins: $sgpr0_sgpr1
79    ; CHECK-NEXT: {{  $}}
80    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
81    ; CHECK-NEXT: [[S_FLBIT_I32_B64_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B64 [[COPY]]
82    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_B64_]]
83    %0:sgpr(s64) = COPY $sgpr0_sgpr1
84    %1:sgpr(s32) = G_CTLZ_ZERO_UNDEF %0
85    S_ENDPGM 0, implicit %1
86...
87