1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX9 %s 3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX11 %s 4 5--- 6name: test_build_vector_trunc_s_v2s16_s_s32_s_s32 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10 11body: | 12 bb.0: 13 liveins: $sgpr0, $sgpr1 14 15 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32 16 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 17 ; GFX9PLUS-NEXT: {{ $}} 18 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 19 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 20 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]] 21 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 22 %0:sgpr(s32) = COPY $sgpr0 23 %1:sgpr(s32) = COPY $sgpr1 24 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 25 S_ENDPGM 0, implicit %2 26... 27 28--- 29name: test_build_vector_trunc_s_pack_lh 30legalized: true 31regBankSelected: true 32tracksRegLiveness: true 33 34body: | 35 bb.0: 36 liveins: $sgpr0, $sgpr1 37 38 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh 39 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 40 ; GFX9PLUS-NEXT: {{ $}} 41 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 42 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 43 ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]] 44 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]] 45 %0:sgpr(s32) = COPY $sgpr0 46 %1:sgpr(s32) = COPY $sgpr1 47 %2:sgpr(s32) = G_CONSTANT i32 16 48 %3:sgpr(s32) = G_LSHR %1, %2 49 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 50 S_ENDPGM 0, implicit %4 51... 52 53# s_pack_hl_b32 was introduced in GFX11 54--- 55name: test_build_vector_trunc_s_pack_hl 56legalized: true 57regBankSelected: true 58tracksRegLiveness: true 59 60body: | 61 bb.0: 62 liveins: $sgpr0, $sgpr1 63 64 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hl 65 ; GFX9: liveins: $sgpr0, $sgpr1 66 ; GFX9-NEXT: {{ $}} 67 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 68 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 69 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 70 ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 71 ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]] 72 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 73 ; 74 ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hl 75 ; GFX11: liveins: $sgpr0, $sgpr1 76 ; GFX11-NEXT: {{ $}} 77 ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 78 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 79 ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY1]], [[COPY]] 80 ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]] 81 %0:sgpr(s32) = COPY $sgpr0 82 %1:sgpr(s32) = COPY $sgpr1 83 %2:sgpr(s32) = G_CONSTANT i32 16 84 %3:sgpr(s32) = G_LSHR %1, %2 85 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0 86 S_ENDPGM 0, implicit %4 87... 88 89--- 90name: test_build_vector_trunc_s_pack_hh 91legalized: true 92regBankSelected: true 93tracksRegLiveness: true 94 95body: | 96 bb.0: 97 liveins: $sgpr0, $sgpr1 98 99 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh 100 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 101 ; GFX9PLUS-NEXT: {{ $}} 102 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 103 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 104 ; GFX9PLUS-NEXT: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]] 105 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]] 106 %0:sgpr(s32) = COPY $sgpr0 107 %1:sgpr(s32) = COPY $sgpr1 108 %2:sgpr(s32) = G_CONSTANT i32 16 109 %3:sgpr(s32) = G_LSHR %0, %2 110 %4:sgpr(s32) = G_LSHR %1, %2 111 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 112 S_ENDPGM 0, implicit %5 113... 114 115# TODO: Should this use an and instead? 116--- 117name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32 118legalized: true 119regBankSelected: true 120tracksRegLiveness: true 121 122body: | 123 bb.0: 124 liveins: $sgpr0 125 126 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32 127 ; GFX9PLUS: liveins: $sgpr0 128 ; GFX9PLUS-NEXT: {{ $}} 129 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 130 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 131 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 132 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 133 %0:sgpr(s32) = COPY $sgpr0 134 %1:sgpr(s32) = G_CONSTANT i32 0 135 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 136 S_ENDPGM 0, implicit %2 137... 138 139--- 140name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32 141legalized: true 142regBankSelected: true 143tracksRegLiveness: true 144 145body: | 146 bb.0: 147 liveins: $sgpr0 148 149 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32 150 ; GFX9PLUS: liveins: $sgpr0 151 ; GFX9PLUS-NEXT: {{ $}} 152 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 153 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 154 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 155 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 156 %0:sgpr(s32) = COPY $sgpr0 157 %1:sgpr(s32) = G_CONSTANT i32 0 158 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0 159 S_ENDPGM 0, implicit %2 160... 161 162--- 163name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32 164legalized: true 165regBankSelected: true 166tracksRegLiveness: true 167 168body: | 169 bb.0: 170 liveins: $sgpr0 171 172 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32 173 ; GFX9PLUS: liveins: $sgpr0 174 ; GFX9PLUS-NEXT: {{ $}} 175 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 176 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]] 177 %0:sgpr(s32) = COPY $sgpr0 178 %1:sgpr(s32) = G_IMPLICIT_DEF 179 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 180 S_ENDPGM 0, implicit %2 181... 182 183--- 184name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32 185legalized: true 186regBankSelected: true 187tracksRegLiveness: true 188 189body: | 190 bb.0: 191 liveins: $sgpr0 192 193 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32 194 ; GFX9PLUS: liveins: $sgpr0 195 ; GFX9PLUS-NEXT: {{ $}} 196 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 197 ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 198 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]] 199 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 200 %0:sgpr(s32) = COPY $sgpr0 201 %1:sgpr(s32) = G_IMPLICIT_DEF 202 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0 203 S_ENDPGM 0, implicit %2 204... 205 206--- 207name: test_build_vector_trunc_s_v2s16_s_undef_s_s32 208legalized: true 209regBankSelected: true 210tracksRegLiveness: true 211 212body: | 213 bb.0: 214 liveins: $sgpr1 215 216 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32 217 ; GFX9PLUS: liveins: $sgpr1 218 ; GFX9PLUS-NEXT: {{ $}} 219 ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 220 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1 221 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]] 222 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 223 %0:sgpr(s32) = G_IMPLICIT_DEF 224 %1:sgpr(s32) = COPY $sgpr1 225 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 226 S_ENDPGM 0, implicit %2 227... 228 229--- 230name: test_build_vector_trunc_s_v2s16_s_s32_undef 231legalized: true 232regBankSelected: true 233tracksRegLiveness: true 234 235body: | 236 bb.0: 237 liveins: $sgpr0 238 239 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef 240 ; GFX9PLUS: liveins: $sgpr0 241 ; GFX9PLUS-NEXT: {{ $}} 242 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 243 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]] 244 %0:sgpr(s32) = COPY $sgpr0 245 %1:sgpr(s32) = G_IMPLICIT_DEF 246 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 247 S_ENDPGM 0, implicit %2 248... 249 250--- 251name: test_build_vector_trunc_s_v2s16_s_zero_s_s32 252legalized: true 253regBankSelected: true 254tracksRegLiveness: true 255 256body: | 257 bb.0: 258 liveins: $sgpr1 259 260 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32 261 ; GFX9PLUS: liveins: $sgpr1 262 ; GFX9PLUS-NEXT: {{ $}} 263 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 264 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1 265 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 266 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 267 %0:sgpr(s32) = G_CONSTANT i32 0 268 %1:sgpr(s32) = COPY $sgpr1 269 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 270 S_ENDPGM 0, implicit %2 271... 272 273--- 274name: test_build_vector_trunc_s_v2s16_s_s32_zero 275legalized: true 276regBankSelected: true 277tracksRegLiveness: true 278 279body: | 280 bb.0: 281 liveins: $sgpr0 282 283 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero 284 ; GFX9PLUS: liveins: $sgpr0 285 ; GFX9PLUS-NEXT: {{ $}} 286 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 287 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 288 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 289 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 290 %0:sgpr(s32) = COPY $sgpr0 291 %1:sgpr(s32) = G_CONSTANT i32 0 292 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 293 S_ENDPGM 0, implicit %2 294... 295 296--- 297name: test_build_vector_trunc_lshr16_zero 298legalized: true 299regBankSelected: true 300tracksRegLiveness: true 301 302body: | 303 bb.0: 304 liveins: $sgpr0 305 306 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_lshr16_zero 307 ; GFX9PLUS: liveins: $sgpr0 308 ; GFX9PLUS-NEXT: {{ $}} 309 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 310 ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def dead $scc 311 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]] 312 %0:sgpr(s32) = G_CONSTANT i32 0 313 %1:sgpr(s32) = COPY $sgpr0 314 %2:sgpr(s32) = G_CONSTANT i32 16 315 %3:sgpr(s32) = G_LSHR %1, %2 316 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0 317 S_ENDPGM 0, implicit %4 318... 319 320# Don't use pack since it would duplicate the shift use 321--- 322name: test_build_vector_trunc_s_pack_lh_multi_use 323legalized: true 324regBankSelected: true 325tracksRegLiveness: true 326 327body: | 328 bb.0: 329 liveins: $sgpr0, $sgpr1 330 331 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use 332 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 333 ; GFX9PLUS-NEXT: {{ $}} 334 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 335 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 336 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 337 ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 338 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]] 339 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]] 340 %0:sgpr(s32) = COPY $sgpr0 341 %1:sgpr(s32) = COPY $sgpr1 342 %2:sgpr(s32) = G_CONSTANT i32 16 343 %3:sgpr(s32) = G_LSHR %1, %2 344 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 345 S_ENDPGM 0, implicit %4, implicit %3 346... 347 348--- 349name: test_build_vector_trunc_s_pack_hh_multi_use_lhs 350legalized: true 351regBankSelected: true 352tracksRegLiveness: true 353 354body: | 355 bb.0: 356 liveins: $sgpr0, $sgpr1 357 358 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs 359 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 360 ; GFX9PLUS-NEXT: {{ $}} 361 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 362 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 363 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 364 ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 365 ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]] 366 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]] 367 %0:sgpr(s32) = COPY $sgpr0 368 %1:sgpr(s32) = COPY $sgpr1 369 %2:sgpr(s32) = G_CONSTANT i32 16 370 %3:sgpr(s32) = G_LSHR %0, %2 371 %4:sgpr(s32) = G_LSHR %1, %2 372 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 373 S_ENDPGM 0, implicit %5, implicit %3 374... 375 376--- 377name: test_build_vector_trunc_s_pack_hh_multi_use_rhs 378legalized: true 379regBankSelected: true 380tracksRegLiveness: true 381 382body: | 383 bb.0: 384 liveins: $sgpr0, $sgpr1 385 386 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs 387 ; GFX9: liveins: $sgpr0, $sgpr1 388 ; GFX9-NEXT: {{ $}} 389 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 390 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 391 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 392 ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 393 ; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 394 ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]] 395 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]] 396 ; 397 ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs 398 ; GFX11: liveins: $sgpr0, $sgpr1 399 ; GFX11-NEXT: {{ $}} 400 ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 401 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 402 ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 403 ; GFX11-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 404 ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY]], [[S_LSHR_B32_]] 405 ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]], implicit [[S_LSHR_B32_]] 406 %0:sgpr(s32) = COPY $sgpr0 407 %1:sgpr(s32) = COPY $sgpr1 408 %2:sgpr(s32) = G_CONSTANT i32 16 409 %3:sgpr(s32) = G_LSHR %0, %2 410 %4:sgpr(s32) = G_LSHR %1, %2 411 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 412 S_ENDPGM 0, implicit %5, implicit %4 413... 414 415--- 416name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt 417legalized: true 418regBankSelected: true 419tracksRegLiveness: true 420 421body: | 422 bb.0: 423 liveins: $sgpr0, $sgpr1 424 425 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt 426 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 427 ; GFX9PLUS-NEXT: {{ $}} 428 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 429 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 430 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15 431 ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 432 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]] 433 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 434 %0:sgpr(s32) = COPY $sgpr0 435 %1:sgpr(s32) = COPY $sgpr1 436 %2:sgpr(s32) = G_CONSTANT i32 15 437 %3:sgpr(s32) = G_LSHR %1, %2 438 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 439 S_ENDPGM 0, implicit %4 440... 441 442--- 443name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt 444legalized: true 445regBankSelected: true 446tracksRegLiveness: true 447 448body: | 449 bb.0: 450 liveins: $sgpr0, $sgpr1 451 452 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt 453 ; GFX9PLUS: liveins: $sgpr0, $sgpr1 454 ; GFX9PLUS-NEXT: {{ $}} 455 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 456 ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 457 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15 458 ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 459 ; GFX9PLUS-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc 460 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]] 461 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 462 %0:sgpr(s32) = COPY $sgpr0 463 %1:sgpr(s32) = COPY $sgpr1 464 %2:sgpr(s32) = G_CONSTANT i32 15 465 %3:sgpr(s32) = G_LSHR %0, %2 466 %4:sgpr(s32) = G_LSHR %1, %2 467 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 468 S_ENDPGM 0, implicit %5 469... 470 471--- 472name: test_build_vector_trunc_s_v2s16_constant_constant 473legalized: true 474regBankSelected: true 475tracksRegLiveness: true 476 477body: | 478 bb.0: 479 480 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant 481 ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 482 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] 483 %0:sgpr(s32) = G_CONSTANT i32 123 484 %1:sgpr(s32) = G_CONSTANT i32 456 485 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 486 S_ENDPGM 0, implicit %2 487... 488 489--- 490name: test_build_vector_trunc_s_v2s16_constant_impdef 491legalized: true 492regBankSelected: true 493tracksRegLiveness: true 494 495body: | 496 bb.0: 497 498 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef 499 ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 500 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] 501 %0:sgpr(s32) = G_CONSTANT i32 123 502 %1:sgpr(s32) = G_IMPLICIT_DEF 503 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 504 S_ENDPGM 0, implicit %2 505... 506 507--- 508name: test_build_vector_trunc_s_v2s16_impdef_constant 509legalized: true 510regBankSelected: true 511tracksRegLiveness: true 512 513body: | 514 bb.0: 515 516 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant 517 ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 518 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 519 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]] 520 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 521 %0:sgpr(s32) = G_IMPLICIT_DEF 522 %1:sgpr(s32) = G_CONSTANT i32 123 523 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 524 S_ENDPGM 0, implicit %2 525... 526 527--- 528name: test_build_vector_trunc_s_v2s16_impdef_impdef 529legalized: true 530regBankSelected: true 531tracksRegLiveness: true 532 533body: | 534 bb.0: 535 536 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef 537 ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 538 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[DEF]] 539 %0:sgpr(s32) = G_IMPLICIT_DEF 540 %1:sgpr(s32) = G_IMPLICIT_DEF 541 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 542 S_ENDPGM 0, implicit %2 543... 544 545--- 546name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant 547legalized: true 548regBankSelected: true 549tracksRegLiveness: true 550 551body: | 552 bb.0: 553 554 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant 555 ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 556 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] 557 %0:sgpr(s16) = G_CONSTANT i16 123 558 %1:sgpr(s16) = G_CONSTANT i16 456 559 %2:sgpr(s32) = G_ZEXT %0 560 %3:sgpr(s32) = G_ZEXT %1 561 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 562 S_ENDPGM 0, implicit %4 563... 564 565--- 566name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant 567legalized: true 568regBankSelected: true 569tracksRegLiveness: true 570 571body: | 572 bb.0: 573 574 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant 575 ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 576 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 577 ; GFX9PLUS-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 578 ; GFX9PLUS-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_1]], [[DEF]], implicit-def dead $scc 579 ; GFX9PLUS-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 580 ; GFX9PLUS-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_MOV_B32_]], implicit-def dead $scc 581 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_AND_B32_]], [[S_AND_B32_1]] 582 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 583 %0:sgpr(s16) = G_IMPLICIT_DEF 584 %1:sgpr(s16) = G_CONSTANT i16 123 585 %2:sgpr(s32) = G_ZEXT %0 586 %3:sgpr(s32) = G_ZEXT %1 587 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 588 S_ENDPGM 0, implicit %4 589... 590 591--- 592name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant 593legalized: true 594regBankSelected: true 595tracksRegLiveness: true 596 597body: | 598 bb.0: 599 600 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant 601 ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208 602 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] 603 %0:sgpr(s16) = G_CONSTANT i16 -16 604 %1:sgpr(s16) = G_CONSTANT i16 -3 605 %2:sgpr(s32) = G_SEXT %0 606 %3:sgpr(s32) = G_SEXT %1 607 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 608 S_ENDPGM 0, implicit %4 609... 610 611--- 612name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant 613legalized: true 614regBankSelected: true 615tracksRegLiveness: true 616 617body: | 618 bb.0: 619 620 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant 621 ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 622 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] 623 %0:sgpr(s16) = G_CONSTANT i16 123 624 %1:sgpr(s16) = G_CONSTANT i16 456 625 %2:sgpr(s32) = G_ANYEXT %0 626 %3:sgpr(s32) = G_ANYEXT %1 627 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 628 S_ENDPGM 0, implicit %4 629... 630 631--- 632name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant 633legalized: true 634regBankSelected: true 635tracksRegLiveness: true 636 637body: | 638 bb.0: 639 640 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant 641 ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 642 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 643 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]] 644 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 645 %0:sgpr(s16) = G_IMPLICIT_DEF 646 %1:sgpr(s16) = G_CONSTANT i16 123 647 %2:sgpr(s32) = G_ANYEXT %0 648 %3:sgpr(s32) = G_ANYEXT %1 649 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 650 S_ENDPGM 0, implicit %4 651... 652 653--- 654name: test_build_vector_trunc_s_v2s16_var_constant 655legalized: true 656regBankSelected: true 657tracksRegLiveness: true 658 659body: | 660 bb.0: 661 liveins: $sgpr0 662 663 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant 664 ; GFX9PLUS: liveins: $sgpr0 665 ; GFX9PLUS-NEXT: {{ $}} 666 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 667 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456 668 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 669 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 670 %0:sgpr(s32) = COPY $sgpr0 671 %1:sgpr(s32) = G_CONSTANT i32 456 672 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 673 S_ENDPGM 0, implicit %2 674... 675 676--- 677name: test_build_vector_trunc_s_v2s16_constant_var 678legalized: true 679regBankSelected: true 680tracksRegLiveness: true 681 682body: | 683 bb.0: 684 liveins: $sgpr0 685 686 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var 687 ; GFX9PLUS: liveins: $sgpr0 688 ; GFX9PLUS-NEXT: {{ $}} 689 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456 690 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 691 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 692 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 693 %0:sgpr(s32) = G_CONSTANT i32 456 694 %1:sgpr(s32) = COPY $sgpr0 695 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 696 S_ENDPGM 0, implicit %2 697... 698 699--- 700name: test_build_vector_trunc_s_v2s16_var_0 701legalized: true 702regBankSelected: true 703tracksRegLiveness: true 704 705body: | 706 bb.0: 707 liveins: $sgpr0 708 709 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_0 710 ; GFX9PLUS: liveins: $sgpr0 711 ; GFX9PLUS-NEXT: {{ $}} 712 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 713 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 714 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 715 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 716 %0:sgpr(s32) = COPY $sgpr0 717 %1:sgpr(s32) = G_CONSTANT i32 0 718 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 719 S_ENDPGM 0, implicit %2 720... 721 722--- 723name: test_build_vector_trunc_s_v2s16_0_var 724legalized: true 725regBankSelected: true 726tracksRegLiveness: true 727 728body: | 729 bb.0: 730 liveins: $sgpr0 731 732 ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_0_var 733 ; GFX9PLUS: liveins: $sgpr0 734 ; GFX9PLUS-NEXT: {{ $}} 735 ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 736 ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 737 ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 738 ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 739 %0:sgpr(s32) = G_CONSTANT i32 0 740 %1:sgpr(s32) = COPY $sgpr0 741 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 742 S_ENDPGM 0, implicit %2 743... 744