1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s 3 4--- 5name: bitreverse_i32_ss 6legalized: true 7regBankSelected: true 8 9body: | 10 bb.0: 11 liveins: $sgpr0 12 ; CHECK-LABEL: name: bitreverse_i32_ss 13 ; CHECK: liveins: $sgpr0 14 ; CHECK-NEXT: {{ $}} 15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 16 ; CHECK-NEXT: [[S_BREV_B32_:%[0-9]+]]:sreg_32 = S_BREV_B32 [[COPY]] 17 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_BREV_B32_]] 18 %0:sgpr(s32) = COPY $sgpr0 19 %1:sgpr(s32) = G_BITREVERSE %0 20 S_ENDPGM 0, implicit %1 21... 22 23--- 24name: bitreverse_i32_vv 25legalized: true 26regBankSelected: true 27 28body: | 29 bb.0: 30 liveins: $vgpr0 31 ; CHECK-LABEL: name: bitreverse_i32_vv 32 ; CHECK: liveins: $vgpr0 33 ; CHECK-NEXT: {{ $}} 34 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 35 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec 36 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]] 37 %0:vgpr(s32) = COPY $vgpr0 38 %1:vgpr(s32) = G_BITREVERSE %0 39 S_ENDPGM 0, implicit %1 40... 41 42--- 43name: bitreverse_i32_vs 44legalized: true 45regBankSelected: true 46 47body: | 48 bb.0: 49 liveins: $sgpr0 50 ; CHECK-LABEL: name: bitreverse_i32_vs 51 ; CHECK: liveins: $sgpr0 52 ; CHECK-NEXT: {{ $}} 53 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 54 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec 55 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]] 56 %0:sgpr(s32) = COPY $sgpr0 57 %1:vgpr(s32) = G_BITREVERSE %0 58 S_ENDPGM 0, implicit %1 59... 60 61--- 62name: bitreverse_i64_ss 63legalized: true 64regBankSelected: true 65 66body: | 67 bb.0: 68 liveins: $sgpr0_sgpr1 69 ; CHECK-LABEL: name: bitreverse_i64_ss 70 ; CHECK: liveins: $sgpr0_sgpr1 71 ; CHECK-NEXT: {{ $}} 72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 73 ; CHECK-NEXT: [[S_BREV_B64_:%[0-9]+]]:sreg_64 = S_BREV_B64 [[COPY]] 74 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_BREV_B64_]] 75 %0:sgpr(s64) = COPY $sgpr0_sgpr1 76 %1:sgpr(s64) = G_BITREVERSE %0 77 S_ENDPGM 0, implicit %1 78... 79 80--- 81name: bitreverse_i64_vv 82legalized: true 83regBankSelected: true 84 85body: | 86 bb.0: 87 liveins: $vgpr0_vgpr1 88 ; CHECK-LABEL: name: bitreverse_i64_vv 89 ; CHECK: liveins: $vgpr0_vgpr1 90 ; CHECK-NEXT: {{ $}} 91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 92 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 93 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 94 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec 95 ; CHECK-NEXT: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec 96 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1 97 ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 98 %0:vgpr(s64) = COPY $vgpr0_vgpr1 99 %2:vgpr(s32), %3:vgpr(s32) = G_UNMERGE_VALUES %0(s64) 100 %4:vgpr(s32) = G_BITREVERSE %3 101 %5:vgpr(s32) = G_BITREVERSE %2 102 %1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32) 103 S_ENDPGM 0, implicit %1 104... 105 106--- 107name: bitreverse_i64_vs 108legalized: true 109regBankSelected: true 110 111body: | 112 bb.0: 113 liveins: $sgpr0_sgpr1 114 ; CHECK-LABEL: name: bitreverse_i64_vs 115 ; CHECK: liveins: $sgpr0_sgpr1 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 119 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 120 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec 121 ; CHECK-NEXT: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec 122 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1 123 ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 124 %0:sgpr(s64) = COPY $sgpr0_sgpr1 125 %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0(s64) 126 %4:vgpr(s32) = G_BITREVERSE %3 127 %5:vgpr(s32) = G_BITREVERSE %2 128 %1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32) 129 S_ENDPGM 0, implicit %1 130... 131