xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
5# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
6
7# GFX6/7 selection should fail.
8# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
9# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
10
11---
12name:            atomicrmw_fadd_s32_local
13legalized:       true
14regBankSelected: true
15tracksRegLiveness: true
16body:             |
17  bb.0:
18    liveins: $vgpr0, $vgpr1
19
20    ; GFX8-LABEL: name: atomicrmw_fadd_s32_local
21    ; GFX8: liveins: $vgpr0, $vgpr1
22    ; GFX8-NEXT: {{  $}}
23    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
24    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
25    ; GFX8-NEXT: $m0 = S_MOV_B32 -1
26    ; GFX8-NEXT: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst (s32), addrspace 3)
27    ; GFX8-NEXT: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
28    ; GFX9-LABEL: name: atomicrmw_fadd_s32_local
29    ; GFX9: liveins: $vgpr0, $vgpr1
30    ; GFX9-NEXT: {{  $}}
31    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
32    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
33    ; GFX9-NEXT: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst (s32), addrspace 3)
34    ; GFX9-NEXT: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
35    ; GFX6-LABEL: name: atomicrmw_fadd_s32_local
36    ; GFX6: liveins: $vgpr0, $vgpr1
37    ; GFX6-NEXT: {{  $}}
38    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
39    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
40    ; GFX6-NEXT: $m0 = S_MOV_B32 -1
41    ; GFX6-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
42    ; GFX6-NEXT: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
43    %0:vgpr(p3) = COPY $vgpr0
44    %1:vgpr(s32) = COPY $vgpr1
45    %2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst (s32), addrspace 3)
46    $vgpr0 = COPY %2
47
48...
49
50---
51name:            atomicrmw_fadd_s32_local_noret
52legalized:       true
53regBankSelected: true
54tracksRegLiveness: true
55body:             |
56  bb.0:
57    liveins: $vgpr0, $vgpr1
58
59    ; GFX8-LABEL: name: atomicrmw_fadd_s32_local_noret
60    ; GFX8: liveins: $vgpr0, $vgpr1
61    ; GFX8-NEXT: {{  $}}
62    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
63    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
64    ; GFX8-NEXT: $m0 = S_MOV_B32 -1
65    ; GFX8-NEXT: DS_ADD_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst (s32), addrspace 3)
66    ; GFX9-LABEL: name: atomicrmw_fadd_s32_local_noret
67    ; GFX9: liveins: $vgpr0, $vgpr1
68    ; GFX9-NEXT: {{  $}}
69    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
70    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
71    ; GFX9-NEXT: DS_ADD_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst (s32), addrspace 3)
72    ; GFX6-LABEL: name: atomicrmw_fadd_s32_local_noret
73    ; GFX6: liveins: $vgpr0, $vgpr1
74    ; GFX6-NEXT: {{  $}}
75    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
76    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
77    ; GFX6-NEXT: $m0 = S_MOV_B32 -1
78    ; GFX6-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
79    %0:vgpr(p3) = COPY $vgpr0
80    %1:vgpr(s32) = COPY $vgpr1
81    %2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst (s32), addrspace 3)
82
83...
84
85---
86name:            atomicrmw_fadd_s32_local_gep4
87legalized:       true
88regBankSelected: true
89tracksRegLiveness: true
90body:             |
91  bb.0:
92    liveins: $vgpr0, $vgpr1
93
94    ; GFX8-LABEL: name: atomicrmw_fadd_s32_local_gep4
95    ; GFX8: liveins: $vgpr0, $vgpr1
96    ; GFX8-NEXT: {{  $}}
97    ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
98    ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
99    ; GFX8-NEXT: $m0 = S_MOV_B32 -1
100    ; GFX8-NEXT: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 4, 0, implicit $m0, implicit $exec :: (load store seq_cst (s32), addrspace 3)
101    ; GFX8-NEXT: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
102    ; GFX9-LABEL: name: atomicrmw_fadd_s32_local_gep4
103    ; GFX9: liveins: $vgpr0, $vgpr1
104    ; GFX9-NEXT: {{  $}}
105    ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
106    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
107    ; GFX9-NEXT: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 4, 0, implicit $exec :: (load store seq_cst (s32), addrspace 3)
108    ; GFX9-NEXT: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
109    ; GFX6-LABEL: name: atomicrmw_fadd_s32_local_gep4
110    ; GFX6: liveins: $vgpr0, $vgpr1
111    ; GFX6-NEXT: {{  $}}
112    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
113    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
114    ; GFX6-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 4
115    ; GFX6-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
116    ; GFX6-NEXT: $m0 = S_MOV_B32 -1
117    ; GFX6-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[PTR_ADD]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
118    ; GFX6-NEXT: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
119    %0:vgpr(p3) = COPY $vgpr0
120    %1:vgpr(s32) = COPY $vgpr1
121    %2:vgpr(s32) = G_CONSTANT i32 4
122    %3:vgpr(p3) = G_PTR_ADD %0, %2
123    %4:vgpr(s32) = G_ATOMICRMW_FADD %3(p3), %1 :: (load store seq_cst (s32), addrspace 3)
124    $vgpr0 = COPY %4
125
126...
127