1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN 3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN 4# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN 5 6--- 7 8name: anyext_sgpr_s16_to_sgpr_s32 9legalized: true 10regBankSelected: true 11body: | 12 bb.0: 13 liveins: $sgpr0 14 15 ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32 16 ; GCN: liveins: $sgpr0 17 ; GCN-NEXT: {{ $}} 18 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 19 ; GCN-NEXT: $sgpr0 = COPY [[COPY]] 20 %0:sgpr(s32) = COPY $sgpr0 21 %1:sgpr(s16) = G_TRUNC %0 22 %2:sgpr(s32) = G_ANYEXT %1 23 $sgpr0 = COPY %2 24 25... 26 27--- 28name: anyext_sgpr_s32_to_sgpr_s64 29legalized: true 30regBankSelected: true 31tracksRegLiveness: true 32body: | 33 bb.0: 34 liveins: $sgpr0 35 36 ; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64 37 ; GCN: liveins: $sgpr0 38 ; GCN-NEXT: {{ $}} 39 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0 40 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF 41 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1 42 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 43 %0:sgpr(s32) = COPY $sgpr0 44 %1:sgpr(s64) = G_ANYEXT %0 45 S_ENDPGM 0, implicit %1 46 47... 48 49--- 50name: anyext_sgpr_s16_to_sgpr_s64 51legalized: true 52regBankSelected: true 53tracksRegLiveness: true 54body: | 55 bb.0: 56 liveins: $sgpr0 57 58 ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64 59 ; GCN: liveins: $sgpr0 60 ; GCN-NEXT: {{ $}} 61 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 62 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 63 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1 64 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 65 %0:sgpr(s32) = COPY $sgpr0 66 %1:sgpr(s16) = G_TRUNC %0 67 %2:sgpr(s64) = G_ANYEXT %1 68 S_ENDPGM 0, implicit %2 69 70... 71 72--- 73name: anyext_vgpr_s32_to_vgpr_s64 74legalized: true 75regBankSelected: true 76tracksRegLiveness: true 77body: | 78 bb.0: 79 liveins: $vgpr0 80 81 ; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64 82 ; GCN: liveins: $vgpr0 83 ; GCN-NEXT: {{ $}} 84 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 85 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF 86 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1 87 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 88 %0:vgpr(s32) = COPY $vgpr0 89 %1:vgpr(s64) = G_ANYEXT %0 90 S_ENDPGM 0, implicit %1 91 92... 93 94--- 95name: anyext_vgpr_s16_to_vgpr_s64 96legalized: true 97regBankSelected: true 98tracksRegLiveness: true 99body: | 100 bb.0: 101 liveins: $vgpr0 102 103 %0:vgpr(s32) = COPY $vgpr0 104 %1:vgpr(s16) = G_TRUNC %0 105 %2:vgpr(s64) = G_ANYEXT %1 106 S_ENDPGM 0, implicit %2 107 108... 109 110# vcc is an invalid extension source 111# --- 112 113# name: anyext_vcc_s1_to_vgpr_s32 114# legalized: true 115# regBankSelected: true 116# body: | 117# bb.0: 118# liveins: $vgpr0 119 120# %0:vgpr(s32) = COPY $vgpr0 121# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0 122# %2:vgpr(s32) = G_ANYEXT %1 123# $vgpr0 = COPY %2 124# ... 125 126--- 127 128name: anyext_sgpr_s1_to_sgpr_s16 129legalized: true 130regBankSelected: true 131body: | 132 bb.0: 133 liveins: $sgpr0 134 135 ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16 136 ; GCN: liveins: $sgpr0 137 ; GCN-NEXT: {{ $}} 138 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 139 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 140 ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc 141 ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]] 142 %0:sgpr(s32) = COPY $sgpr0 143 %1:sgpr(s1) = G_TRUNC %0 144 %2:sgpr(s16) = G_ANYEXT %1 145 %3:sgpr(s32) = G_ZEXT %2 146 $sgpr0 = COPY %3 147... 148 149--- 150 151name: anyext_sgpr_s1_to_sgpr_s32 152legalized: true 153regBankSelected: true 154body: | 155 bb.0: 156 liveins: $sgpr0 157 158 ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32 159 ; GCN: liveins: $sgpr0 160 ; GCN-NEXT: {{ $}} 161 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 162 ; GCN-NEXT: $sgpr0 = COPY [[COPY]] 163 %0:sgpr(s32) = COPY $sgpr0 164 %1:sgpr(s1) = G_TRUNC %0 165 %2:sgpr(s32) = G_ANYEXT %1 166 $sgpr0 = COPY %2 167... 168 169--- 170 171name: anyext_sgpr_s1_to_sgpr_s64 172legalized: true 173regBankSelected: true 174body: | 175 bb.0: 176 liveins: $sgpr0 177 178 ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64 179 ; GCN: liveins: $sgpr0 180 ; GCN-NEXT: {{ $}} 181 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 182 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 183 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1 184 ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]] 185 %0:sgpr(s32) = COPY $sgpr0 186 %1:sgpr(s1) = G_TRUNC %0 187 %2:sgpr(s64) = G_ANYEXT %1 188 $sgpr0_sgpr1 = COPY %2 189... 190 191--- 192 193name: anyext_vgpr_s1_to_vgpr_s16 194legalized: true 195regBankSelected: true 196body: | 197 bb.0: 198 liveins: $vgpr0 199 200 ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s16 201 ; GCN: liveins: $vgpr0 202 ; GCN-NEXT: {{ $}} 203 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 204 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 205 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec 206 ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]] 207 %0:vgpr(s32) = COPY $vgpr0 208 %1:vgpr(s1) = G_TRUNC %0 209 %2:vgpr(s16) = G_ANYEXT %1 210 %3:vgpr(s32) = G_ZEXT %2 211 $vgpr0 = COPY %3 212... 213 214--- 215 216name: anyext_vgpr_s1_to_vgpr_s32 217legalized: true 218regBankSelected: true 219body: | 220 bb.0: 221 liveins: $vgpr0 222 223 ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32 224 ; GCN: liveins: $vgpr0 225 ; GCN-NEXT: {{ $}} 226 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 227 ; GCN-NEXT: $vgpr0 = COPY [[COPY]] 228 %0:vgpr(s32) = COPY $vgpr0 229 %1:vgpr(s1) = G_TRUNC %0 230 %2:vgpr(s32) = G_ANYEXT %1 231 $vgpr0 = COPY %2 232... 233 234--- 235 236name: anyext_sgpr_s1_to_vgpr_s32 237legalized: true 238regBankSelected: true 239body: | 240 bb.0: 241 liveins: $sgpr0 242 243 ; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32 244 ; GCN: liveins: $sgpr0 245 ; GCN-NEXT: {{ $}} 246 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 247 ; GCN-NEXT: $sgpr0 = COPY [[COPY]] 248 %0:sgpr(s32) = COPY $sgpr0 249 %1:sgpr(s1) = G_TRUNC %0 250 %2:sgpr(s32) = G_ANYEXT %1 251 $sgpr0 = COPY %2 252... 253 254--- 255 256name: anyext_vgpr_s16_to_vgpr_s32 257legalized: true 258regBankSelected: true 259body: | 260 bb.0: 261 liveins: $vgpr0 262 263 ; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32 264 ; GCN: liveins: $vgpr0 265 ; GCN-NEXT: {{ $}} 266 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 267 ; GCN-NEXT: $vgpr0 = COPY [[COPY]] 268 %0:vgpr(s32) = COPY $vgpr0 269 %1:vgpr(s16) = G_TRUNC %0 270 %2:vgpr(s32) = G_ANYEXT %1 271 $vgpr0 = COPY %2 272 273... 274 275# The source register already has an assigned register class that 276# should not be interpreted as vcc. 277--- 278 279name: anyext_regclass_sgpr_s1_to_sgpr_s32 280legalized: true 281regBankSelected: true 282body: | 283 bb.0: 284 liveins: $sgpr0 285 286 ; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32 287 ; GCN: liveins: $sgpr0 288 ; GCN-NEXT: {{ $}} 289 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 290 ; GCN-NEXT: $sgpr0 = COPY [[COPY]] 291 %0:sgpr(s32) = COPY $sgpr0 292 %1:sreg_32(s1) = G_TRUNC %0 293 %2:sgpr(s32) = G_ANYEXT %1 294 $sgpr0 = COPY %2 295... 296