1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s 4 5# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:sgpr(s16) (in function: sin_s16_vs) 6# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:vgpr(s16) (in function: sin_s16_vv) 7 8--- 9name: sin_s16_vs 10legalized: true 11regBankSelected: true 12tracksRegLiveness: true 13 14body: | 15 bb.0: 16 liveins: $sgpr0 17 18 ; CHECK-LABEL: name: sin_s16_vs 19 ; CHECK: liveins: $sgpr0 20 ; CHECK-NEXT: {{ $}} 21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 22 ; CHECK-NEXT: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 23 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] 24 %0:sgpr(s32) = COPY $sgpr0 25 %1:sgpr(s16) = G_TRUNC %0 26 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1 27 S_ENDPGM 0, implicit %2 28... 29 30--- 31name: sin_s16_vv 32legalized: true 33regBankSelected: true 34tracksRegLiveness: true 35 36body: | 37 bb.0: 38 liveins: $vgpr0 39 40 ; CHECK-LABEL: name: sin_s16_vv 41 ; CHECK: liveins: $vgpr0 42 ; CHECK-NEXT: {{ $}} 43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 44 ; CHECK-NEXT: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 45 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] 46 %0:vgpr(s32) = COPY $vgpr0 47 %1:vgpr(s16) = G_TRUNC %0 48 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1 49 S_ENDPGM 0, implicit %2 50... 51