1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 4 5--- 6name: sin_s32_vs 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10 11body: | 12 bb.0: 13 liveins: $sgpr0 14 15 ; CHECK-LABEL: name: sin_s32_vs 16 ; CHECK: liveins: $sgpr0 17 ; CHECK-NEXT: {{ $}} 18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 19 ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 20 ; CHECK-NEXT: S_ENDPGM 0, implicit %1 21 %0:sgpr(s32) = COPY $sgpr0 22 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0 23 S_ENDPGM 0, implicit %1 24... 25 26--- 27name: sin_s32_vv 28legalized: true 29regBankSelected: true 30tracksRegLiveness: true 31 32body: | 33 bb.0: 34 liveins: $vgpr0 35 36 ; CHECK-LABEL: name: sin_s32_vv 37 ; CHECK: liveins: $vgpr0 38 ; CHECK-NEXT: {{ $}} 39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 40 ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 41 ; CHECK-NEXT: S_ENDPGM 0, implicit %1 42 %0:vgpr(s32) = COPY $vgpr0 43 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0 44 S_ENDPGM 0, implicit %1 45... 46