xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN
3
4---
5
6name: s_barrier
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10
11
12body: |
13  bb.0:
14    ; GCN-LABEL: name: s_barrier
15    ; GCN: S_BARRIER
16    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.barrier)
17
18
19...
20