xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
4
5---
6name: rcp_s32_vs
7legalized: true
8regBankSelected: true
9tracksRegLiveness: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0
14
15    ; CHECK-LABEL: name: rcp_s32_vs
16    ; CHECK: liveins: $sgpr0
17    ; CHECK-NEXT: {{  $}}
18    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19    ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20    ; CHECK-NEXT: S_ENDPGM 0, implicit %1
21    %0:sgpr(s32) = COPY $sgpr0
22    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
23    S_ENDPGM 0, implicit %1
24...
25
26---
27name: rcp_s32_vv
28legalized: true
29regBankSelected: true
30tracksRegLiveness: true
31
32body: |
33  bb.0:
34    liveins: $vgpr0
35
36    ; CHECK-LABEL: name: rcp_s32_vv
37    ; CHECK: liveins: $vgpr0
38    ; CHECK-NEXT: {{  $}}
39    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40    ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41    ; CHECK-NEXT: S_ENDPGM 0, implicit %1
42    %0:vgpr(s32) = COPY $vgpr0
43    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
44    S_ENDPGM 0, implicit %1
45...
46
47---
48name: rcp_s64_vs
49legalized: true
50regBankSelected: true
51tracksRegLiveness: true
52
53body: |
54  bb.0:
55    liveins: $sgpr0_sgpr1
56
57    ; CHECK-LABEL: name: rcp_s64_vs
58    ; CHECK: liveins: $sgpr0_sgpr1
59    ; CHECK-NEXT: {{  $}}
60    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
61    ; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62    ; CHECK-NEXT: S_ENDPGM 0, implicit %1
63    %0:sgpr(s64) = COPY $sgpr0_sgpr1
64    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
65    S_ENDPGM 0, implicit %1
66...
67
68---
69name: rcp_s64_vv
70legalized: true
71regBankSelected: true
72tracksRegLiveness: true
73
74body: |
75  bb.0:
76    liveins: $vgpr0_vgpr1
77
78    ; CHECK-LABEL: name: rcp_s64_vv
79    ; CHECK: liveins: $vgpr0_vgpr1
80    ; CHECK-NEXT: {{  $}}
81    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
82    ; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83    ; CHECK-NEXT: S_ENDPGM 0, implicit %1
84    %0:vgpr(s64) = COPY $vgpr0_vgpr1
85    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
86    S_ENDPGM 0, implicit %1
87...
88