xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
3
4---
5name: mul_u24_vsv
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0, $vgpr0
13    ; GCN-LABEL: name: mul_u24_vsv
14    ; GCN: liveins: $sgpr0, $vgpr0
15    ; GCN-NEXT: {{  $}}
16    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
17    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; GCN-NEXT: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
19    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
20    %0:sgpr(s32) = COPY $sgpr0
21    %1:vgpr(s32) = COPY $vgpr0
22    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
23    S_ENDPGM 0, implicit %2
24...
25
26---
27name: mul_u24_vvs
28legalized: true
29regBankSelected: true
30tracksRegLiveness: true
31
32body: |
33  bb.0:
34    liveins: $sgpr0, $vgpr0
35    ; GCN-LABEL: name: mul_u24_vvs
36    ; GCN: liveins: $sgpr0, $vgpr0
37    ; GCN-NEXT: {{  $}}
38    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
39    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
40    ; GCN-NEXT: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
41    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
42    %0:vgpr(s32) = COPY $vgpr0
43    %1:sgpr(s32) = COPY $sgpr0
44    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
45    S_ENDPGM 0, implicit %2
46...
47
48---
49name: mul_u24_vvv
50legalized: true
51regBankSelected: true
52tracksRegLiveness: true
53
54body: |
55  bb.0:
56    liveins: $vgpr0, $vgpr1
57    ; GCN-LABEL: name: mul_u24_vvv
58    ; GCN: liveins: $vgpr0, $vgpr1
59    ; GCN-NEXT: {{  $}}
60    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
61    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
62    ; GCN-NEXT: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
63    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
64    %0:vgpr(s32) = COPY $vgpr0
65    %1:vgpr(s32) = COPY $vgpr1
66    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
67    S_ENDPGM 0, implicit %2
68...
69