xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5
6name: ds_swizzle_0
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10
11
12body: |
13  bb.0:
14    liveins: $vgpr0
15    ; CHECK-LABEL: name: ds_swizzle_0
16    ; CHECK: liveins: $vgpr0
17    ; CHECK-NEXT: {{  $}}
18    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; CHECK-NEXT: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 0, 0, implicit $exec
20    ; CHECK-NEXT: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
21    %0:vgpr(s32) = COPY $vgpr0
22    %1:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0
23    S_ENDPGM 0, implicit %1
24
25...
26
27---
28
29name: ds_swizzle_65535
30legalized:       true
31regBankSelected: true
32tracksRegLiveness: true
33
34
35body: |
36  bb.0:
37    liveins: $vgpr0
38    ; CHECK-LABEL: name: ds_swizzle_65535
39    ; CHECK: liveins: $vgpr0
40    ; CHECK-NEXT: {{  $}}
41    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
42    ; CHECK-NEXT: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 65535, 0, implicit $exec
43    ; CHECK-NEXT: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
44    %0:vgpr(s32) = COPY $vgpr0
45    %1:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), %0, 65535
46    S_ENDPGM 0, implicit %1
47
48...
49