1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s 3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s 4 5# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s 6 7# SI-ERR-NOT: remark 8# SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv) 9# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs) 10# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv) 11# SI-ERR-NOT: remark 12 13--- 14name: class_s16_vcc_sv 15legalized: true 16regBankSelected: true 17tracksRegLiveness: true 18 19body: | 20 bb.0: 21 liveins: $sgpr0, $vgpr0 22 ; WAVE32-LABEL: name: class_s16_vcc_sv 23 ; WAVE32: liveins: $sgpr0, $vgpr0 24 ; WAVE32-NEXT: {{ $}} 25 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 26 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 27 ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec 28 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] 29 ; WAVE64-LABEL: name: class_s16_vcc_sv 30 ; WAVE64: liveins: $sgpr0, $vgpr0 31 ; WAVE64-NEXT: {{ $}} 32 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 33 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 34 ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec 35 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] 36 %0:sgpr(s32) = COPY $sgpr0 37 %1:vgpr(s32) = COPY $vgpr0 38 %2:sgpr(s16) = G_TRUNC %0 39 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 40 S_ENDPGM 0, implicit %4 41... 42 43--- 44name: class_s16_vcc_vs 45legalized: true 46regBankSelected: true 47tracksRegLiveness: true 48 49body: | 50 bb.0: 51 liveins: $sgpr0, $vgpr0 52 ; WAVE32-LABEL: name: class_s16_vcc_vs 53 ; WAVE32: liveins: $sgpr0, $vgpr0 54 ; WAVE32-NEXT: {{ $}} 55 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 56 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 57 ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec 58 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] 59 ; WAVE64-LABEL: name: class_s16_vcc_vs 60 ; WAVE64: liveins: $sgpr0, $vgpr0 61 ; WAVE64-NEXT: {{ $}} 62 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 63 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 64 ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec 65 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] 66 %0:vgpr(s32) = COPY $vgpr0 67 %1:sgpr(s32) = COPY $sgpr0 68 %2:vgpr(s16) = G_TRUNC %0 69 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 70 S_ENDPGM 0, implicit %4 71... 72 73--- 74name: class_s16_vcc_vv 75legalized: true 76regBankSelected: true 77tracksRegLiveness: true 78 79body: | 80 bb.0: 81 liveins: $vgpr0, $vgpr1 82 ; WAVE32-LABEL: name: class_s16_vcc_vv 83 ; WAVE32: liveins: $vgpr0, $vgpr1 84 ; WAVE32-NEXT: {{ $}} 85 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 86 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 87 ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec 88 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] 89 ; WAVE64-LABEL: name: class_s16_vcc_vv 90 ; WAVE64: liveins: $vgpr0, $vgpr1 91 ; WAVE64-NEXT: {{ $}} 92 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 93 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 94 ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec 95 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] 96 %0:vgpr(s32) = COPY $vgpr0 97 %1:vgpr(s32) = COPY $vgpr1 98 %2:vgpr(s16) = G_TRUNC %0 99 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 100 S_ENDPGM 0, implicit %4 101... 102