xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=WAVE64 %s
3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=WAVE32 %s
4
5---
6name: class_s32_vcc_sv
7legalized: true
8regBankSelected: true
9tracksRegLiveness: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $vgpr0
14    ; WAVE64-LABEL: name: class_s32_vcc_sv
15    ; WAVE64: liveins: $sgpr0, $vgpr0
16    ; WAVE64-NEXT: {{  $}}
17    ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
20    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
21    ; WAVE32-LABEL: name: class_s32_vcc_sv
22    ; WAVE32: liveins: $sgpr0, $vgpr0
23    ; WAVE32-NEXT: {{  $}}
24    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
25    ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
26    ; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
27    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
28    %0:sgpr(s32) = COPY $sgpr0
29    %1:vgpr(s32) = COPY $vgpr0
30    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
31    S_ENDPGM 0, implicit %2
32...
33
34---
35name: class_s32_vcc_vs
36legalized: true
37regBankSelected: true
38tracksRegLiveness: true
39
40body: |
41  bb.0:
42    liveins: $sgpr0, $vgpr0
43    ; WAVE64-LABEL: name: class_s32_vcc_vs
44    ; WAVE64: liveins: $sgpr0, $vgpr0
45    ; WAVE64-NEXT: {{  $}}
46    ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
47    ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
48    ; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
49    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
50    ; WAVE32-LABEL: name: class_s32_vcc_vs
51    ; WAVE32: liveins: $sgpr0, $vgpr0
52    ; WAVE32-NEXT: {{  $}}
53    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
54    ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
55    ; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
56    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
57    %0:vgpr(s32) = COPY $vgpr0
58    %1:sgpr(s32) = COPY $sgpr0
59    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
60    S_ENDPGM 0, implicit %2
61...
62
63---
64name: class_s32_vcc_vv
65legalized: true
66regBankSelected: true
67tracksRegLiveness: true
68
69body: |
70  bb.0:
71    liveins: $vgpr0, $vgpr1
72    ; WAVE64-LABEL: name: class_s32_vcc_vv
73    ; WAVE64: liveins: $vgpr0, $vgpr1
74    ; WAVE64-NEXT: {{  $}}
75    ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
76    ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
77    ; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
78    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
79    ; WAVE32-LABEL: name: class_s32_vcc_vv
80    ; WAVE32: liveins: $vgpr0, $vgpr1
81    ; WAVE32-NEXT: {{  $}}
82    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
83    ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
84    ; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
85    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
86    %0:vgpr(s32) = COPY $vgpr0
87    %1:vgpr(s32) = COPY $vgpr1
88    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
89    S_ENDPGM 0, implicit %2
90...
91
92---
93name: class_s64_vcc_sv
94legalized: true
95regBankSelected: true
96tracksRegLiveness: true
97
98body: |
99  bb.0:
100    liveins: $sgpr0_sgpr1, $vgpr0
101    ; WAVE64-LABEL: name: class_s64_vcc_sv
102    ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
103    ; WAVE64-NEXT: {{  $}}
104    ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
105    ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
106    ; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
107    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
108    ; WAVE32-LABEL: name: class_s64_vcc_sv
109    ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
110    ; WAVE32-NEXT: {{  $}}
111    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
112    ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
113    ; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
114    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
115    %0:sgpr(s64) = COPY $sgpr0_sgpr1
116    %1:vgpr(s32) = COPY $vgpr0
117    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
118    S_ENDPGM 0, implicit %2
119...
120
121---
122name: class_s64_vcc_vs
123legalized: true
124regBankSelected: true
125tracksRegLiveness: true
126
127body: |
128  bb.0:
129    liveins: $sgpr0_sgpr1, $vgpr0
130
131    ; WAVE64-LABEL: name: class_s64_vcc_vs
132    ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
133    ; WAVE64-NEXT: {{  $}}
134    ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
135    ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
136    ; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
137    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
138    ; WAVE32-LABEL: name: class_s64_vcc_vs
139    ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
140    ; WAVE32-NEXT: {{  $}}
141    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
142    ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
143    ; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
144    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
145    %0:vgpr(s64) = COPY $vgpr0_vgpr1
146    %1:sgpr(s32) = COPY $sgpr0
147    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
148    S_ENDPGM 0, implicit %2
149...
150
151---
152name: class_s64_vcc_vv
153legalized: true
154regBankSelected: true
155tracksRegLiveness: true
156
157body: |
158  bb.0:
159    liveins: $vgpr0_vgpr1, $vgpr2
160
161    ; WAVE64-LABEL: name: class_s64_vcc_vv
162    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
163    ; WAVE64-NEXT: {{  $}}
164    ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
165    ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
166    ; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
167    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
168    ; WAVE32-LABEL: name: class_s64_vcc_vv
169    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
170    ; WAVE32-NEXT: {{  $}}
171    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
172    ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
173    ; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
174    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
175    %0:vgpr(s64) = COPY $vgpr0_vgpr1
176    %1:vgpr(s32) = COPY $vgpr2
177    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
178    S_ENDPGM 0, implicit %2
179...
180