1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s 3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s 4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s 5# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s 6# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s 7 8--- 9name: add_s32 10legalized: true 11regBankSelected: true 12 13body: | 14 bb.0: 15 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 16 17 18 ; GFX6-LABEL: name: add_s32 19 ; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 20 ; GFX6-NEXT: {{ $}} 21 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 22 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 23 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 24 ; GFX6-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc 25 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec 26 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_ADD_I32_]], [[V_ADD_CO_U32_e64_]], 0, implicit $exec 27 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_4:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_5:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_ADD_CO_U32_e64_2]], [[COPY2]], 0, implicit $exec 28 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_CO_U32_e64_]], implicit [[V_ADD_CO_U32_e64_2]], implicit [[V_ADD_CO_U32_e64_4]] 29 ; 30 ; GFX9-LABEL: name: add_s32 31 ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 32 ; GFX9-NEXT: {{ $}} 33 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 34 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 35 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 36 ; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc 37 ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec 38 ; GFX9-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec 39 ; GFX9-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec 40 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]] 41 %0:sgpr(s32) = COPY $sgpr0 42 %1:sgpr(s32) = COPY $sgpr1 43 %2:vgpr(s32) = COPY $vgpr0 44 %3:vgpr(p1) = COPY $vgpr3_vgpr4 45 %4:sgpr(s32) = G_CONSTANT i32 1 46 %5:sgpr(s32) = G_CONSTANT i32 4096 47 48 %6:sgpr(s32) = G_ADD %0, %1 49 50 %7:vgpr(s32) = G_ADD %2, %6 51 52 %8:vgpr(s32) = G_ADD %6, %7 53 54 %9:vgpr(s32) = G_ADD %8, %2 55 56 S_ENDPGM 0, implicit %6, implicit %7, implicit %8, implicit %9 57 58... 59 60--- 61name: add_neg_inline_const_64_to_sub_s32_s 62legalized: true 63regBankSelected: true 64tracksRegLiveness: true 65 66body: | 67 bb.0: 68 liveins: $sgpr0 69 70 ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s 71 ; GFX6: liveins: $sgpr0 72 ; GFX6-NEXT: {{ $}} 73 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 74 ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc 75 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]] 76 ; 77 ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s 78 ; GFX9: liveins: $sgpr0 79 ; GFX9-NEXT: {{ $}} 80 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 81 ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc 82 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]] 83 %0:sgpr(s32) = COPY $sgpr0 84 %1:sgpr(s32) = G_CONSTANT i32 -64 85 %2:sgpr(s32) = G_ADD %0, %1 86 S_ENDPGM 0, implicit %2 87 88... 89 90--- 91name: add_neg_inline_const_64_to_sub_s32_v 92legalized: true 93regBankSelected: true 94tracksRegLiveness: true 95 96body: | 97 bb.0: 98 liveins: $vgpr0 99 100 ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v 101 ; GFX6: liveins: $vgpr0 102 ; GFX6-NEXT: {{ $}} 103 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 104 ; GFX6-NEXT: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_SUB_CO_U32_e64 [[COPY]], 64, 0, implicit $exec 105 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]] 106 ; 107 ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v 108 ; GFX9: liveins: $vgpr0 109 ; GFX9-NEXT: {{ $}} 110 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 111 ; GFX9-NEXT: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec 112 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]] 113 %0:vgpr(s32) = COPY $vgpr0 114 %1:vgpr(s32) = G_CONSTANT i32 -64 115 %2:vgpr(s32) = G_ADD %0, %1 116 S_ENDPGM 0, implicit %2 117 118... 119 120--- 121name: add_neg_inline_const_16_to_sub_s32_s 122legalized: true 123regBankSelected: true 124tracksRegLiveness: true 125 126body: | 127 bb.0: 128 liveins: $sgpr0 129 130 ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s 131 ; GFX6: liveins: $sgpr0 132 ; GFX6-NEXT: {{ $}} 133 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 134 ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 135 ; GFX6-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 136 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]] 137 ; 138 ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s 139 ; GFX9: liveins: $sgpr0 140 ; GFX9-NEXT: {{ $}} 141 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 142 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 143 ; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc 144 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]] 145 %0:sgpr(s32) = COPY $sgpr0 146 %1:sgpr(s32) = G_CONSTANT i32 16 147 %2:sgpr(s32) = G_ADD %0, %1 148 S_ENDPGM 0, implicit %2 149 150... 151 152--- 153name: add_neg_inline_const_16_to_sub_s32_v 154legalized: true 155regBankSelected: true 156tracksRegLiveness: true 157 158body: | 159 bb.0: 160 liveins: $vgpr0 161 162 ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v 163 ; GFX6: liveins: $vgpr0 164 ; GFX6-NEXT: {{ $}} 165 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 166 ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec 167 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec 168 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]] 169 ; 170 ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v 171 ; GFX9: liveins: $vgpr0 172 ; GFX9-NEXT: {{ $}} 173 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 174 ; GFX9-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec 175 ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec 176 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]] 177 %0:vgpr(s32) = COPY $vgpr0 178 %1:vgpr(s32) = G_CONSTANT i32 16 179 %2:vgpr(s32) = G_ADD %0, %1 180 S_ENDPGM 0, implicit %2 181 182... 183