1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=WAVE64 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=WAVE32 %s 4 5define amdgpu_ps void @i1_vcc_to_vcc_copy(i32 %val, float %a0, float %a1, float %b0, float %b1) { 6; WAVE64-LABEL: i1_vcc_to_vcc_copy: 7; WAVE64: ; %bb.0: ; %main_body 8; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 9; WAVE64-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 10; WAVE64-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc 11; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm 12; WAVE64-NEXT: s_endpgm 13; 14; WAVE32-LABEL: i1_vcc_to_vcc_copy: 15; WAVE32: ; %bb.0: ; %main_body 16; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 17; WAVE32-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo 18; WAVE32-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo 19; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm 20; WAVE32-NEXT: s_endpgm 21main_body: 22 %vcc = icmp eq i32 %val, 2 23 %a = select i1 %vcc, float %a0, float %a1 24 %b = select i1 %vcc, float %b0, float %b1 25 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true) 26 ret void 27} 28 29define amdgpu_ps void @i1_sgpr_to_vcc_copy(i32 inreg %val, float %a0, float %a1, float %b0, float %b1) { 30; WAVE64-LABEL: i1_sgpr_to_vcc_copy: 31; WAVE64: ; %bb.0: ; %main_body 32; WAVE64-NEXT: s_cmp_eq_u32 s0, 2 33; WAVE64-NEXT: s_cselect_b32 s0, 1, 0 34; WAVE64-NEXT: s_and_b32 s0, 1, s0 35; WAVE64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 36; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 37; WAVE64-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc 38; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm 39; WAVE64-NEXT: s_endpgm 40; 41; WAVE32-LABEL: i1_sgpr_to_vcc_copy: 42; WAVE32: ; %bb.0: ; %main_body 43; WAVE32-NEXT: s_cmp_eq_u32 s0, 2 44; WAVE32-NEXT: s_cselect_b32 s0, 1, 0 45; WAVE32-NEXT: s_and_b32 s0, 1, s0 46; WAVE32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 47; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo 48; WAVE32-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo 49; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm 50; WAVE32-NEXT: s_endpgm 51main_body: 52 %uniform_i1 = icmp eq i32 %val, 2 53 %a = select i1 %uniform_i1, float %a0, float %a1 54 %b = select i1 %uniform_i1, float %b0, float %b1 55 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true) 56 ret void 57} 58 59declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) 60