xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll (revision 8e68c1204580d0bb57001929d3345af80b27ac01) 
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -amdgpu-enable-remove-incompatible-functions=0 -mtriple=amdgcn-amd-amdhsa -stop-after=legalizer -o - %s | FileCheck %s
3
4; Make sure legalizer info doesn't assert on dummy targets
5
6define i16 @vop3p_add_i16(i16 %arg0) #0 {
7  ; CHECK-LABEL: name: vop3p_add_i16
8  ; CHECK: bb.1 (%ir-block.0):
9  ; CHECK-NEXT:   liveins: $vgpr0
10  ; CHECK-NEXT: {{  $}}
11  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
13  ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
14  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
15  ; CHECK-NEXT:   $vgpr0 = COPY [[ANYEXT]](s32)
16  ; CHECK-NEXT:   SI_RETURN implicit $vgpr0
17  %add = add i16 %arg0, %arg0
18  ret i16 %add
19}
20
21define <2 x i16> @vop3p_add_v2i16(<2 x i16> %arg0) #0 {
22  ; CHECK-LABEL: name: vop3p_add_v2i16
23  ; CHECK: bb.1 (%ir-block.0):
24  ; CHECK-NEXT:   liveins: $vgpr0
25  ; CHECK-NEXT: {{  $}}
26  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
27  ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
28  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
29  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
30  ; CHECK-NEXT:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
31  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
32  ; CHECK-NEXT:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
33  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
34  ; CHECK-NEXT:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
35  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
36  ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC2]]
37  ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC3]]
38  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16)
39  ; CHECK-NEXT:   [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16)
40  ; CHECK-NEXT:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
41  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
42  ; CHECK-NEXT:   [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
43  ; CHECK-NEXT:   $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
44  ; CHECK-NEXT:   SI_RETURN implicit $vgpr0
45  %add = add <2 x i16> %arg0, %arg0
46  ret <2 x i16> %add
47}
48
49define i16 @halfinsts_add_i16(i16 %arg0) #1 {
50  ; CHECK-LABEL: name: halfinsts_add_i16
51  ; CHECK: bb.1 (%ir-block.0):
52  ; CHECK-NEXT:   liveins: $vgpr0
53  ; CHECK-NEXT: {{  $}}
54  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
55  ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
56  ; CHECK-NEXT:   $vgpr0 = COPY [[ADD]](s32)
57  ; CHECK-NEXT:   SI_RETURN implicit $vgpr0
58  %add = add i16 %arg0, %arg0
59  ret i16 %add
60}
61
62define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {
63  ; CHECK-LABEL: name: halfinsts_add_v2i16
64  ; CHECK: bb.1 (%ir-block.0):
65  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1
66  ; CHECK-NEXT: {{  $}}
67  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
68  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
69  ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
70  ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY1]]
71  ; CHECK-NEXT:   $vgpr0 = COPY [[ADD]](s32)
72  ; CHECK-NEXT:   $vgpr1 = COPY [[ADD1]](s32)
73  ; CHECK-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
74  %add = add <2 x i16> %arg0, %arg0
75  ret <2 x i16> %add
76}
77
78attributes #0 = { "target-features"="+vop3p" }
79attributes #0 = { "target-features"="+16-bit-insts" }
80