1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s 3 4--- 5name: temporal_divergent_i32 6legalized: true 7tracksRegLiveness: true 8body: | 9 ; GFX10-LABEL: name: temporal_divergent_i32 10 ; GFX10: bb.0: 11 ; GFX10-NEXT: successors: %bb.1(0x80000000) 12 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 13 ; GFX10-NEXT: {{ $}} 14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 15 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 16 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 17 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) 18 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 19 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 20 ; GFX10-NEXT: {{ $}} 21 ; GFX10-NEXT: bb.1: 22 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) 23 ; GFX10-NEXT: {{ $}} 24 ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C]](s32), %bb.0 25 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 26 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 27 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C2]] 28 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[ADD]](s32) 29 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] 30 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) 31 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 32 ; GFX10-NEXT: G_BR %bb.2 33 ; GFX10-NEXT: {{ $}} 34 ; GFX10-NEXT: bb.2: 35 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.1 36 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.1 37 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s32) 38 ; GFX10-NEXT: G_STORE [[PHI2]](s32), [[MV]](p0) :: (store (s32)) 39 ; GFX10-NEXT: SI_RETURN 40 bb.0: 41 successors: %bb.1(0x80000000) 42 liveins: $vgpr0, $vgpr1, $vgpr2 43 44 %0:_(s32) = COPY $vgpr0 45 %1:_(s32) = COPY $vgpr1 46 %2:_(s32) = COPY $vgpr2 47 %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) 48 %4:_(s32) = G_CONSTANT i32 0 49 %5:_(s32) = G_CONSTANT i32 -1 50 51 bb.1: 52 successors: %bb.2(0x04000000), %bb.1(0x7c000000) 53 54 %6:_(s32) = G_PHI %7(s32), %bb.1, %4(s32), %bb.0 55 %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 56 %10:_(s32) = G_CONSTANT i32 1 57 %9:_(s32) = G_ADD %8, %10 58 %11:_(s32) = G_UITOFP %9(s32) 59 %12:_(s1) = G_FCMP floatpred(ogt), %11(s32), %0 60 %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %12(s1), %6(s32) 61 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 62 G_BR %bb.2 63 64 bb.2: 65 %13:_(s32) = G_PHI %9(s32), %bb.1 66 %14:_(s32) = G_PHI %7(s32), %bb.1 67 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s32) 68 G_STORE %13(s32), %3(p0) :: (store (s32)) 69 SI_RETURN 70... 71