xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir (revision 17006033f9c763b80b1f59cb015cdbe934268b70) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
3
4---
5name: urem_s32_var_const0
6tracksRegLiveness: true
7body:             |
8  bb.0:
9    liveins: $vgpr0
10
11    ; GCN-LABEL: name: urem_s32_var_const0
12    ; GCN: liveins: $vgpr0
13    ; GCN-NEXT: {{  $}}
14    ; GCN-NEXT: %var:_(s32) = COPY $vgpr0
15    ; GCN-NEXT: %const:_(s32) = G_CONSTANT i32 0
16    ; GCN-NEXT: %rem:_(s32) = G_UREM %var, %const
17    ; GCN-NEXT: $vgpr0 = COPY %rem(s32)
18    %var:_(s32) = COPY $vgpr0
19    %const:_(s32) = G_CONSTANT i32 0
20    %rem:_(s32) = G_UREM %var, %const
21    $vgpr0 = COPY %rem
22...
23
24---
25name: urem_s32_var_const1
26tracksRegLiveness: true
27body:             |
28  bb.0:
29    liveins: $vgpr0
30
31    ; GCN-LABEL: name: urem_s32_var_const1
32    ; GCN: liveins: $vgpr0
33    ; GCN-NEXT: {{  $}}
34    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
35    ; GCN-NEXT: $vgpr0 = COPY [[C]](s32)
36    %var:_(s32) = COPY $vgpr0
37    %const:_(s32) = G_CONSTANT i32 1
38    %rem:_(s32) = G_UREM %var, %const
39    $vgpr0 = COPY %rem
40...
41
42---
43name: urem_s32_var_const2
44tracksRegLiveness: true
45body:             |
46  bb.0:
47    liveins: $vgpr0
48
49    ; GCN-LABEL: name: urem_s32_var_const2
50    ; GCN: liveins: $vgpr0
51    ; GCN-NEXT: {{  $}}
52    ; GCN-NEXT: %var:_(s32) = COPY $vgpr0
53    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
54    ; GCN-NEXT: %rem:_(s32) = G_AND %var, [[C]]
55    ; GCN-NEXT: $vgpr0 = COPY %rem(s32)
56    %var:_(s32) = COPY $vgpr0
57    %const:_(s32) = G_CONSTANT i32 2
58    %rem:_(s32) = G_UREM %var, %const
59    $vgpr0 = COPY %rem
60...
61
62---
63name: urem_s32_var_shl1
64tracksRegLiveness: true
65body:             |
66  bb.0:
67    liveins: $vgpr0, $vgpr1
68
69    ; GCN-LABEL: name: urem_s32_var_shl1
70    ; GCN: liveins: $vgpr0, $vgpr1
71    ; GCN-NEXT: {{  $}}
72    ; GCN-NEXT: %var:_(s32) = COPY $vgpr0
73    ; GCN-NEXT: %shift_amt:_(s32) = COPY $vgpr1
74    ; GCN-NEXT: %one:_(s32) = G_CONSTANT i32 1
75    ; GCN-NEXT: %one_bit:_(s32) = G_SHL %one, %shift_amt(s32)
76    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
77    ; GCN-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %one_bit, [[C]]
78    ; GCN-NEXT: %rem:_(s32) = G_AND %var, [[ADD]]
79    ; GCN-NEXT: $vgpr0 = COPY %rem(s32)
80    %var:_(s32) = COPY $vgpr0
81    %shift_amt:_(s32) = COPY $vgpr1
82    %one:_(s32) = G_CONSTANT i32 1
83    %one_bit:_(s32) = G_SHL %one, %shift_amt
84    %rem:_(s32) = G_UREM %var, %one_bit
85    $vgpr0 = COPY %rem
86...
87
88---
89name: urem_s64_var_shl1
90tracksRegLiveness: true
91body:             |
92  bb.0:
93    liveins: $vgpr0_vgpr1, $vgpr2
94
95    ; GCN-LABEL: name: urem_s64_var_shl1
96    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2
97    ; GCN-NEXT: {{  $}}
98    ; GCN-NEXT: %var:_(s64) = COPY $vgpr0_vgpr1
99    ; GCN-NEXT: %shiftamt:_(s32) = COPY $vgpr2
100    ; GCN-NEXT: %one:_(s64) = G_CONSTANT i64 1
101    ; GCN-NEXT: %one_bit:_(s64) = G_SHL %one, %shiftamt(s32)
102    ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
103    ; GCN-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %one_bit, [[C]]
104    ; GCN-NEXT: %rem:_(s64) = G_AND %var, [[ADD]]
105    ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(s64)
106    %var:_(s64) = COPY $vgpr0_vgpr1
107    %shiftamt:_(s32) = COPY $vgpr2
108    %one:_(s64) = G_CONSTANT i64 1
109    %one_bit:_(s64) = G_SHL %one, %shiftamt
110    %rem:_(s64) = G_UREM %var, %one_bit
111    $vgpr0_vgpr1 = COPY %rem
112...
113
114---
115name: urem_v2s32_var_shl1
116tracksRegLiveness: true
117body:             |
118  bb.0:
119    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
120
121    ; GCN-LABEL: name: urem_v2s32_var_shl1
122    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
123    ; GCN-NEXT: {{  $}}
124    ; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
125    ; GCN-NEXT: %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
126    ; GCN-NEXT: %one:_(s32) = G_CONSTANT i32 1
127    ; GCN-NEXT: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32)
128    ; GCN-NEXT: %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt(<2 x s32>)
129    ; GCN-NEXT: %rem:_(<2 x s32>) = G_UREM %var, %one_bit
130    ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
131    %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
132    %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
133    %one:_(s32) = G_CONSTANT i32 1
134    %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one
135    %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt
136    %rem:_(<2 x s32>) = G_UREM %var, %one_bit
137    $vgpr0_vgpr1 = COPY %rem
138...
139
140---
141name: urem_v2s16_var_const4_build_vector_trunc
142tracksRegLiveness: true
143body:             |
144  bb.0:
145    liveins: $vgpr0, $vgpr1
146
147    ; GCN-LABEL: name: urem_v2s16_var_const4_build_vector_trunc
148    ; GCN: liveins: $vgpr0, $vgpr1
149    ; GCN-NEXT: {{  $}}
150    ; GCN-NEXT: %var:_(<2 x s16>) = COPY $vgpr0
151    ; GCN-NEXT: %four:_(s32) = G_CONSTANT i32 4
152    ; GCN-NEXT: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %four(s32)
153    ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
154    ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
155    ; GCN-NEXT: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD %four_vec, [[BUILD_VECTOR]]
156    ; GCN-NEXT: %rem:_(<2 x s16>) = G_AND %var, [[ADD]]
157    ; GCN-NEXT: $vgpr0 = COPY %rem(<2 x s16>)
158    %var:_(<2 x s16>) = COPY $vgpr0
159    %shift_amt:_(s32) = COPY $vgpr1
160    %four:_(s32) = G_CONSTANT i32 4
161    %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %four
162    %rem:_(<2 x s16>) = G_UREM %var, %four_vec
163    $vgpr0 = COPY %rem
164...
165
166# The shl is a known power of two, but we do not know if the final
167# value is a power of 2 due to the truncation.
168---
169name: urem_v2s16_var_nonconst_build_vector_trunc
170tracksRegLiveness: true
171body:             |
172  bb.0:
173    liveins: $vgpr0, $vgpr1
174
175    ; GCN-LABEL: name: urem_v2s16_var_nonconst_build_vector_trunc
176    ; GCN: liveins: $vgpr0, $vgpr1
177    ; GCN-NEXT: {{  $}}
178    ; GCN-NEXT: %var:_(<2 x s16>) = COPY $vgpr0
179    ; GCN-NEXT: %shift_amt:_(s32) = COPY $vgpr1
180    ; GCN-NEXT: %two:_(s32) = G_CONSTANT i32 2
181    ; GCN-NEXT: %four:_(s32) = G_CONSTANT i32 4
182    ; GCN-NEXT: %shift:_(s32) = G_SHL %two, %shift_amt(s32)
183    ; GCN-NEXT: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %shift(s32)
184    ; GCN-NEXT: %rem:_(<2 x s16>) = G_UREM %var, %four_vec
185    ; GCN-NEXT: $vgpr0 = COPY %rem(<2 x s16>)
186    %var:_(<2 x s16>) = COPY $vgpr0
187    %shift_amt:_(s32) = COPY $vgpr1
188    %two:_(s32) = G_CONSTANT i32 2
189    %four:_(s32) = G_CONSTANT i32 4
190    %shift:_(s32) = G_SHL %two, %shift_amt
191    %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %shift
192    %rem:_(<2 x s16>) = G_UREM %var, %four_vec
193    $vgpr0 = COPY %rem
194...
195
196---
197name: v_urem_v2i32_pow2k_denom
198tracksRegLiveness: true
199body:             |
200  bb.0:
201    liveins: $vgpr0_vgpr1
202
203    ; GCN-LABEL: name: v_urem_v2i32_pow2k_denom
204    ; GCN: liveins: $vgpr0_vgpr1
205    ; GCN-NEXT: {{  $}}
206    ; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
207    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4095
208    ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
209    ; GCN-NEXT: %rem:_(<2 x s32>) = G_AND %var, [[BUILD_VECTOR]]
210    ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
211    %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
212    %pow2:_(s32) = G_CONSTANT i32 4096
213    %pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2(s32), %pow2(s32)
214    %rem:_(<2 x s32>) = G_UREM %var, %pow2_vec
215    $vgpr0_vgpr1 = COPY %rem
216...
217
218---
219name: v_urem_v2i32_pow2k_not_splat_denom
220tracksRegLiveness: true
221body:             |
222  bb.0:
223    liveins: $vgpr0_vgpr1
224
225    ; GCN-LABEL: name: v_urem_v2i32_pow2k_not_splat_denom
226    ; GCN: liveins: $vgpr0_vgpr1
227    ; GCN-NEXT: {{  $}}
228    ; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
229    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4095
230    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
231    ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)
232    ; GCN-NEXT: %rem:_(<2 x s32>) = G_AND %var, [[BUILD_VECTOR]]
233    ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
234    %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
235    %pow2_1:_(s32) = G_CONSTANT i32 4096
236    %pow2_2:_(s32) = G_CONSTANT i32 2048
237    %pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2_1(s32), %pow2_2(s32)
238    %rem:_(<2 x s32>) = G_UREM %var, %pow2_vec
239    $vgpr0_vgpr1 = COPY %rem
240...
241
242---
243name: v_urem_v2i64_pow2k_denom
244tracksRegLiveness: true
245body:             |
246  bb.0:
247    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
248
249    ; GCN-LABEL: name: v_urem_v2i64_pow2k_denom
250    ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
251    ; GCN-NEXT: {{  $}}
252    ; GCN-NEXT: %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
253    ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4095
254    ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
255    ; GCN-NEXT: %rem:_(<2 x s64>) = G_AND %var, [[BUILD_VECTOR]]
256    ; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %rem(<2 x s64>)
257    %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
258    %pow2:_(s64) = G_CONSTANT i64 4096
259    %pow2_vec:_(<2 x s64>) = G_BUILD_VECTOR %pow2(s64), %pow2(s64)
260    %rem:_(<2 x s64>) = G_UREM %var, %pow2_vec
261    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %rem
262...
263