1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s 3 4 5--- 6name: narrow_shl_s64_32_s64amt 7tracksRegLiveness: true 8body: | 9 bb.0: 10 liveins: $vgpr0_vgpr1 11 12 ; CHECK-LABEL: name: narrow_shl_s64_32_s64amt 13 ; CHECK: liveins: $vgpr0_vgpr1 14 ; CHECK-NEXT: {{ $}} 15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 16 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 17 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 18 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32) 19 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 20 %0:_(s64) = COPY $vgpr0_vgpr1 21 %1:_(s64) = G_CONSTANT i64 32 22 %2:_(s64) = G_SHL %0, %1 23 $vgpr0_vgpr1 = COPY %2 24... 25 26--- 27name: narrow_shl_s64_32 28tracksRegLiveness: true 29body: | 30 bb.0: 31 liveins: $vgpr0_vgpr1 32 33 ; CHECK-LABEL: name: narrow_shl_s64_32 34 ; CHECK: liveins: $vgpr0_vgpr1 35 ; CHECK-NEXT: {{ $}} 36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 37 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 38 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 39 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32) 40 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 41 %0:_(s64) = COPY $vgpr0_vgpr1 42 %1:_(s32) = G_CONSTANT i32 32 43 %2:_(s64) = G_SHL %0, %1 44 $vgpr0_vgpr1 = COPY %2 45... 46 47--- 48name: narrow_shl_s64_33 49tracksRegLiveness: true 50body: | 51 bb.0: 52 liveins: $vgpr0_vgpr1 53 54 ; CHECK-LABEL: name: narrow_shl_s64_33 55 ; CHECK: liveins: $vgpr0_vgpr1 56 ; CHECK-NEXT: {{ $}} 57 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 58 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 59 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 60 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) 61 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 62 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32) 63 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 64 %0:_(s64) = COPY $vgpr0_vgpr1 65 %1:_(s32) = G_CONSTANT i32 33 66 %2:_(s64) = G_SHL %0, %1 67 $vgpr0_vgpr1 = COPY %2 68... 69 70--- 71name: narrow_shl_s64_31 72tracksRegLiveness: true 73body: | 74 bb.0: 75 liveins: $vgpr0_vgpr1 76 77 ; CHECK-LABEL: name: narrow_shl_s64_31 78 ; CHECK: liveins: $vgpr0_vgpr1 79 ; CHECK-NEXT: {{ $}} 80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 81 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 82 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) 83 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64) 84 %0:_(s64) = COPY $vgpr0_vgpr1 85 %1:_(s32) = G_CONSTANT i32 31 86 %2:_(s64) = G_SHL %0, %1 87 $vgpr0_vgpr1 = COPY %2 88... 89 90--- 91name: narrow_shl_s64_63 92tracksRegLiveness: true 93body: | 94 bb.0: 95 liveins: $vgpr0_vgpr1 96 97 ; CHECK-LABEL: name: narrow_shl_s64_63 98 ; CHECK: liveins: $vgpr0_vgpr1 99 ; CHECK-NEXT: {{ $}} 100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 101 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 102 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 103 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) 104 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 105 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32) 106 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 107 %0:_(s64) = COPY $vgpr0_vgpr1 108 %1:_(s32) = G_CONSTANT i32 63 109 %2:_(s64) = G_SHL %0, %1 110 $vgpr0_vgpr1 = COPY %2 111... 112 113--- 114name: narrow_shl_s64_64 115tracksRegLiveness: true 116body: | 117 bb.0: 118 liveins: $vgpr0_vgpr1 119 120 ; CHECK-LABEL: name: narrow_shl_s64_64 121 ; CHECK: liveins: $vgpr0_vgpr1 122 ; CHECK-NEXT: {{ $}} 123 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF 124 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64) 125 %0:_(s64) = COPY $vgpr0_vgpr1 126 %1:_(s32) = G_CONSTANT i32 64 127 %2:_(s64) = G_SHL %0, %1 128 $vgpr0_vgpr1 = COPY %2 129... 130 131--- 132name: narrow_shl_s64_65 133tracksRegLiveness: true 134body: | 135 bb.0: 136 liveins: $vgpr0_vgpr1 137 138 ; CHECK-LABEL: name: narrow_shl_s64_65 139 ; CHECK: liveins: $vgpr0_vgpr1 140 ; CHECK-NEXT: {{ $}} 141 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF 142 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64) 143 %0:_(s64) = COPY $vgpr0_vgpr1 144 %1:_(s32) = G_CONSTANT i32 65 145 %2:_(s64) = G_SHL %0, %1 146 $vgpr0_vgpr1 = COPY %2 147... 148 149--- 150name: narrow_shl_s32_16 151tracksRegLiveness: true 152body: | 153 bb.0: 154 liveins: $vgpr0 155 156 ; CHECK-LABEL: name: narrow_shl_s32_16 157 ; CHECK: liveins: $vgpr0 158 ; CHECK-NEXT: {{ $}} 159 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 160 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 161 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) 162 ; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32) 163 %0:_(s32) = COPY $vgpr0 164 %1:_(s32) = G_CONSTANT i32 16 165 %2:_(s32) = G_SHL %0, %1 166 $vgpr0 = COPY %2 167... 168 169--- 170name: narrow_shl_s32_17 171tracksRegLiveness: true 172body: | 173 bb.0: 174 liveins: $vgpr0 175 176 ; CHECK-LABEL: name: narrow_shl_s32_17 177 ; CHECK: liveins: $vgpr0 178 ; CHECK-NEXT: {{ $}} 179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 180 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 181 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) 182 ; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32) 183 %0:_(s32) = COPY $vgpr0 184 %1:_(s32) = G_CONSTANT i32 17 185 %2:_(s32) = G_SHL %0, %1 186 $vgpr0 = COPY %2 187... 188 189--- 190name: narrow_shl_v2s32_17 191tracksRegLiveness: true 192body: | 193 bb.0: 194 liveins: $vgpr0_vgpr1 195 196 ; CHECK-LABEL: name: narrow_shl_v2s32_17 197 ; CHECK: liveins: $vgpr0_vgpr1 198 ; CHECK-NEXT: {{ $}} 199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 200 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 201 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32) 202 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s32>) 203 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](<2 x s32>) 204 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 205 %1:_(s32) = G_CONSTANT i32 17 206 %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1 207 %3:_(<2 x s32>) = G_SHL %0, %2 208 $vgpr0_vgpr1 = COPY %3 209... 210