xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            test_add_rhs
6body:             |
7  bb.0:
8    liveins: $vgpr0, $vgpr1
9
10    ; CHECK-LABEL: name: test_add_rhs
11    ; CHECK: liveins: $vgpr0, $vgpr1
12    ; CHECK-NEXT: {{  $}}
13    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
14    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
15    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
16    ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
17    %0:_(s32) = COPY $vgpr0
18    %1:_(s32) = COPY $vgpr1
19    %2:_(s32) = G_FNEG %1
20    %3:_(s32) = G_FADD %0, %2
21    $vgpr0 = COPY %3(s32)
22
23...
24---
25name:            test_add_lhs
26body:             |
27  bb.0:
28    liveins: $vgpr0, $vgpr1
29
30    ; CHECK-LABEL: name: test_add_lhs
31    ; CHECK: liveins: $vgpr0, $vgpr1
32    ; CHECK-NEXT: {{  $}}
33    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
34    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
35    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY1]], [[COPY]]
36    ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
37    %0:_(s32) = COPY $vgpr0
38    %1:_(s32) = COPY $vgpr1
39    %2:_(s32) = G_FNEG %0
40    %3:_(s32) = G_FADD %2, %1
41    $vgpr0 = COPY %3(s32)
42
43...
44---
45name:            test_sub
46body:             |
47  bb.0:
48    liveins: $vgpr0, $vgpr1
49
50    ; CHECK-LABEL: name: test_sub
51    ; CHECK: liveins: $vgpr0, $vgpr1
52    ; CHECK-NEXT: {{  $}}
53    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
54    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
55    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
56    ; CHECK-NEXT: $vgpr0 = COPY [[FADD]](s32)
57    %0:_(s32) = COPY $vgpr0
58    %1:_(s32) = COPY $vgpr1
59    %2:_(s32) = G_FNEG %1
60    %3:_(s32) = G_FSUB %0, %2
61    $vgpr0 = COPY %3(s32)
62
63...
64---
65name:            test_mul
66body:             |
67  bb.0:
68    liveins: $vgpr0, $vgpr1
69
70    ; CHECK-LABEL: name: test_mul
71    ; CHECK: liveins: $vgpr0, $vgpr1
72    ; CHECK-NEXT: {{  $}}
73    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
74    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
75    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
76    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
77    %0:_(s32) = COPY $vgpr0
78    %1:_(s32) = COPY $vgpr1
79    %2:_(s32) = G_FNEG %0
80    %3:_(s32) = G_FNEG %1
81    %4:_(s32) = G_FMUL %2, %3
82    $vgpr0 = COPY %4(s32)
83
84...
85---
86name:            test_div
87body:             |
88  bb.0:
89    liveins: $vgpr0, $vgpr1
90
91    ; CHECK-LABEL: name: test_div
92    ; CHECK: liveins: $vgpr0, $vgpr1
93    ; CHECK-NEXT: {{  $}}
94    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
95    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
96    ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
97    ; CHECK-NEXT: $vgpr0 = COPY [[FDIV]](s32)
98    %0:_(s32) = COPY $vgpr0
99    %1:_(s32) = COPY $vgpr1
100    %2:_(s32) = G_FNEG %0
101    %3:_(s32) = G_FNEG %1
102    %4:_(s32) = G_FDIV %2, %3
103    $vgpr0 = COPY %4(s32)
104
105...
106---
107name:            test_fmad
108body:             |
109  bb.0:
110    liveins: $vgpr0, $vgpr1, $vgpr2
111
112    ; CHECK-LABEL: name: test_fmad
113    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
114    ; CHECK-NEXT: {{  $}}
115    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
116    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
117    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
118    ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
119    ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32)
120    %0:_(s32) = COPY $vgpr0
121    %1:_(s32) = COPY $vgpr1
122    %2:_(s32) = COPY $vgpr2
123    %3:_(s32) = G_FNEG %0
124    %4:_(s32) = G_FNEG %1
125    %5:_(s32) = G_FMAD %3, %4, %2
126    $vgpr0 = COPY %5(s32)
127
128...
129---
130name:            test_fma
131body:             |
132  bb.0:
133    liveins: $vgpr0, $vgpr1, $vgpr2
134
135    ; CHECK-LABEL: name: test_fma
136    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
137    ; CHECK-NEXT: {{  $}}
138    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
139    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
140    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
141    ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
142    ; CHECK-NEXT: $vgpr0 = COPY [[FMA]](s32)
143    %0:_(s32) = COPY $vgpr0
144    %1:_(s32) = COPY $vgpr1
145    %2:_(s32) = COPY $vgpr2
146    %3:_(s32) = G_FNEG %0
147    %4:_(s32) = G_FNEG %1
148    %5:_(s32) = G_FMA %3, %4, %2
149    $vgpr0 = COPY %5(s32)
150
151...
152