xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir (revision ac321cbb0350996ceef4e6d9e8a1035880609288)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4# Tries to emit a foldable G_PTR_ADD with (p1, s32) operands.
5---
6name:            test_ptradd_crash__offset_smaller
7tracksRegLiveness: true
8body:             |
9  bb.0:
10    ; CHECK-LABEL: name: test_ptradd_crash__offset_smaller
11    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
12    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64)
13    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1)
14    ; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
15    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
16    %1:_(p1) = G_CONSTANT i64 0
17    %3:_(s32) = G_CONSTANT i32 3
18    %0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
19    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
20    $sgpr0 = COPY %2
21    SI_RETURN_TO_EPILOG implicit $sgpr0
22...
23
24# Tries to emit a foldable G_PTR_ADD with (p1, s128) operands.
25---
26name:            test_ptradd_crash__offset_wider
27tracksRegLiveness: true
28body:             |
29  bb.0:
30    ; CHECK-LABEL: name: test_ptradd_crash__offset_wider
31    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
32    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64)
33    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1)
34    ; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
35    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
36    %1:_(p1) = G_CONSTANT i64 0
37    %3:_(s32) = G_CONSTANT i32 3
38    %0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
39    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
40    $sgpr0 = COPY %2
41    SI_RETURN_TO_EPILOG implicit $sgpr0
42...
43