1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: narrow_ashr_s64_32_s64amt 6tracksRegLiveness: true 7body: | 8 bb.0: 9 liveins: $vgpr0_vgpr1 10 11 ; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt 12 ; CHECK: liveins: $vgpr0_vgpr1 13 ; CHECK-NEXT: {{ $}} 14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 15 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 16 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 17 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) 18 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32) 19 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 20 %0:_(s64) = COPY $vgpr0_vgpr1 21 %1:_(s64) = G_CONSTANT i64 32 22 %2:_(s64) = G_ASHR %0, %1 23 $vgpr0_vgpr1 = COPY %2 24... 25 26--- 27name: narrow_ashr_s64_32 28tracksRegLiveness: true 29body: | 30 bb.0: 31 liveins: $vgpr0_vgpr1 32 33 ; CHECK-LABEL: name: narrow_ashr_s64_32 34 ; CHECK: liveins: $vgpr0_vgpr1 35 ; CHECK-NEXT: {{ $}} 36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 37 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 38 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 39 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) 40 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32) 41 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 42 %0:_(s64) = COPY $vgpr0_vgpr1 43 %1:_(s32) = G_CONSTANT i32 32 44 %2:_(s64) = G_ASHR %0, %1 45 $vgpr0_vgpr1 = COPY %2 46... 47 48--- 49name: narrow_ashr_s64_33 50tracksRegLiveness: true 51body: | 52 bb.0: 53 liveins: $vgpr0_vgpr1 54 55 ; CHECK-LABEL: name: narrow_ashr_s64_33 56 ; CHECK: liveins: $vgpr0_vgpr1 57 ; CHECK-NEXT: {{ $}} 58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 59 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 60 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 61 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) 62 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 63 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32) 64 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32) 65 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 66 %0:_(s64) = COPY $vgpr0_vgpr1 67 %1:_(s32) = G_CONSTANT i32 33 68 %2:_(s64) = G_ASHR %0, %1 69 $vgpr0_vgpr1 = COPY %2 70... 71 72--- 73name: narrow_ashr_s64_31 74tracksRegLiveness: true 75body: | 76 bb.0: 77 liveins: $vgpr0_vgpr1 78 79 ; CHECK-LABEL: name: narrow_ashr_s64_31 80 ; CHECK: liveins: $vgpr0_vgpr1 81 ; CHECK-NEXT: {{ $}} 82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 83 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 84 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32) 85 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64) 86 %0:_(s64) = COPY $vgpr0_vgpr1 87 %1:_(s32) = G_CONSTANT i32 31 88 %2:_(s64) = G_ASHR %0, %1 89 $vgpr0_vgpr1 = COPY %2 90... 91 92--- 93name: narrow_ashr_s64_63 94tracksRegLiveness: true 95body: | 96 bb.0: 97 liveins: $vgpr0_vgpr1 98 99 ; CHECK-LABEL: name: narrow_ashr_s64_63 100 ; CHECK: liveins: $vgpr0_vgpr1 101 ; CHECK-NEXT: {{ $}} 102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 103 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 104 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 105 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) 106 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32) 107 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64) 108 %0:_(s64) = COPY $vgpr0_vgpr1 109 %1:_(s32) = G_CONSTANT i32 63 110 %2:_(s64) = G_ASHR %0, %1 111 $vgpr0_vgpr1 = COPY %2 112... 113 114--- 115name: narrow_ashr_s64_64 116tracksRegLiveness: true 117body: | 118 bb.0: 119 liveins: $vgpr0_vgpr1 120 121 ; CHECK-LABEL: name: narrow_ashr_s64_64 122 ; CHECK: liveins: $vgpr0_vgpr1 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF 125 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64) 126 %0:_(s64) = COPY $vgpr0_vgpr1 127 %1:_(s32) = G_CONSTANT i32 64 128 %2:_(s64) = G_ASHR %0, %1 129 $vgpr0_vgpr1 = COPY %2 130... 131 132--- 133name: narrow_ashr_s64_65 134tracksRegLiveness: true 135body: | 136 bb.0: 137 liveins: $vgpr0_vgpr1 138 139 ; CHECK-LABEL: name: narrow_ashr_s64_65 140 ; CHECK: liveins: $vgpr0_vgpr1 141 ; CHECK-NEXT: {{ $}} 142 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF 143 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64) 144 %0:_(s64) = COPY $vgpr0_vgpr1 145 %1:_(s32) = G_CONSTANT i32 65 146 %2:_(s64) = G_ASHR %0, %1 147 $vgpr0_vgpr1 = COPY %2 148... 149 150--- 151name: narrow_ashr_s32_16 152tracksRegLiveness: true 153body: | 154 bb.0: 155 liveins: $vgpr0 156 157 ; CHECK-LABEL: name: narrow_ashr_s32_16 158 ; CHECK: liveins: $vgpr0 159 ; CHECK-NEXT: {{ $}} 160 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 161 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 162 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) 163 ; CHECK-NEXT: $vgpr0 = COPY [[ASHR]](s32) 164 %0:_(s32) = COPY $vgpr0 165 %1:_(s32) = G_CONSTANT i32 16 166 %2:_(s32) = G_ASHR %0, %1 167 $vgpr0 = COPY %2 168... 169 170--- 171name: narrow_ashr_s32_17 172tracksRegLiveness: true 173body: | 174 bb.0: 175 liveins: $vgpr0 176 177 ; CHECK-LABEL: name: narrow_ashr_s32_17 178 ; CHECK: liveins: $vgpr0 179 ; CHECK-NEXT: {{ $}} 180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 181 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 182 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) 183 ; CHECK-NEXT: $vgpr0 = COPY [[ASHR]](s32) 184 %0:_(s32) = COPY $vgpr0 185 %1:_(s32) = G_CONSTANT i32 17 186 %2:_(s32) = G_ASHR %0, %1 187 $vgpr0 = COPY %2 188... 189 190--- 191name: narrow_ashr_v2s32_17 192tracksRegLiveness: true 193body: | 194 bb.0: 195 liveins: $vgpr0_vgpr1 196 197 ; CHECK-LABEL: name: narrow_ashr_v2s32_17 198 ; CHECK: liveins: $vgpr0_vgpr1 199 ; CHECK-NEXT: {{ $}} 200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 202 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32) 203 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR]](<2 x s32>) 204 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](<2 x s32>) 205 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 206 %1:_(s32) = G_CONSTANT i32 17 207 %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1 208 %3:_(<2 x s32>) = G_ASHR %0, %2 209 $vgpr0_vgpr1 = COPY %3 210... 211