1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=instruction-select < %s | FileCheck --check-prefix=GFX9 %s 3 4define ptr @buffer_load_p0(ptr addrspace(8) inreg %buf) { 5 ; GFX9-LABEL: name: buffer_load_p0 6 ; GFX9: bb.1 (%ir-block.0): 7 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 8 ; GFX9-NEXT: {{ $}} 9 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 10 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 11 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 12 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 13 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 14 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 15 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s64) from %ir.buf, align 1, addrspace 8) 16 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub0 17 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub1 18 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]] 19 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]] 20 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 21 %ret = call ptr @llvm.amdgcn.raw.ptr.buffer.load.p0(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 22 ret ptr %ret 23} 24 25define void @buffer_store_p0(ptr %data, ptr addrspace(8) inreg %buf) { 26 ; GFX9-LABEL: name: buffer_store_p0 27 ; GFX9: bb.1 (%ir-block.0): 28 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1 29 ; GFX9-NEXT: {{ $}} 30 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 31 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 32 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 33 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr16 34 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr17 35 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr18 36 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr19 37 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 38 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 39 ; GFX9-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into %ir.buf, align 1, addrspace 8) 40 ; GFX9-NEXT: SI_RETURN 41 call void @llvm.amdgcn.raw.ptr.buffer.store.p0(ptr %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 42 ret void 43} 44 45define ptr addrspace(1) @buffer_load_p1(ptr addrspace(8) inreg %buf) { 46 ; GFX9-LABEL: name: buffer_load_p1 47 ; GFX9: bb.1 (%ir-block.0): 48 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 49 ; GFX9-NEXT: {{ $}} 50 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 51 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 52 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 53 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 54 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 55 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 56 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s64) from %ir.buf, align 1, addrspace 8) 57 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub0 58 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub1 59 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]] 60 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]] 61 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 62 %ret = call ptr addrspace(1) @llvm.amdgcn.raw.ptr.buffer.load.p1(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 63 ret ptr addrspace(1) %ret 64} 65 66define void @buffer_store_p1(ptr addrspace(1) %data, ptr addrspace(8) inreg %buf) { 67 ; GFX9-LABEL: name: buffer_store_p1 68 ; GFX9: bb.1 (%ir-block.0): 69 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1 70 ; GFX9-NEXT: {{ $}} 71 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 72 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 73 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 74 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr16 75 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr17 76 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr18 77 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr19 78 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 79 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 80 ; GFX9-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into %ir.buf, align 1, addrspace 8) 81 ; GFX9-NEXT: SI_RETURN 82 call void @llvm.amdgcn.raw.ptr.buffer.store.p1(ptr addrspace(1) %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 83 ret void 84} 85 86define ptr addrspace(4) @buffer_load_p4(ptr addrspace(8) inreg %buf) { 87 ; GFX9-LABEL: name: buffer_load_p4 88 ; GFX9: bb.1 (%ir-block.0): 89 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 90 ; GFX9-NEXT: {{ $}} 91 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 92 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 93 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 94 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 95 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 96 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 97 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s64) from %ir.buf, align 1, addrspace 8) 98 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub0 99 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub1 100 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]] 101 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]] 102 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 103 %ret = call ptr addrspace(4) @llvm.amdgcn.raw.ptr.buffer.load.p4(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 104 ret ptr addrspace(4) %ret 105} 106 107define void @buffer_store_p4(ptr addrspace(4) %data, ptr addrspace(8) inreg %buf) { 108 ; GFX9-LABEL: name: buffer_store_p4 109 ; GFX9: bb.1 (%ir-block.0): 110 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1 111 ; GFX9-NEXT: {{ $}} 112 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 113 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 114 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 115 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr16 116 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr17 117 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr18 118 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr19 119 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 120 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 121 ; GFX9-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into %ir.buf, align 1, addrspace 8) 122 ; GFX9-NEXT: SI_RETURN 123 call void @llvm.amdgcn.raw.ptr.buffer.store.p4(ptr addrspace(4) %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 124 ret void 125} 126 127define ptr addrspace(5) @buffer_load_p5(ptr addrspace(8) inreg %buf) { 128 ; GFX9-LABEL: name: buffer_load_p5 129 ; GFX9: bb.1 (%ir-block.0): 130 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 131 ; GFX9-NEXT: {{ $}} 132 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 133 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 134 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 135 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 136 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 137 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 138 ; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.buf, align 1, addrspace 8) 139 ; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]] 140 ; GFX9-NEXT: SI_RETURN implicit $vgpr0 141 %ret = call ptr addrspace(5) @llvm.amdgcn.raw.ptr.buffer.load.p5(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 142 ret ptr addrspace(5) %ret 143} 144 145define void @buffer_store_p5(ptr addrspace(5) %data, ptr addrspace(8) inreg %buf) { 146 ; GFX9-LABEL: name: buffer_store_p5 147 ; GFX9: bb.1 (%ir-block.0): 148 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0 149 ; GFX9-NEXT: {{ $}} 150 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 151 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16 152 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17 153 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr18 154 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr19 155 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 156 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 157 ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s32) into %ir.buf, align 1, addrspace 8) 158 ; GFX9-NEXT: SI_RETURN 159 call void @llvm.amdgcn.raw.ptr.buffer.store.p5(ptr addrspace(5) %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 160 ret void 161} 162 163define <2 x ptr addrspace(1)> @buffer_load_v2p1(ptr addrspace(8) inreg %buf) { 164 ; GFX9-LABEL: name: buffer_load_v2p1 165 ; GFX9: bb.1 (%ir-block.0): 166 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 167 ; GFX9-NEXT: {{ $}} 168 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 169 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 170 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 171 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 172 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 173 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 174 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x s64>) from %ir.buf, align 1, addrspace 8) 175 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub0 176 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub1 177 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub2 178 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub3 179 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]] 180 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]] 181 ; GFX9-NEXT: $vgpr2 = COPY [[COPY6]] 182 ; GFX9-NEXT: $vgpr3 = COPY [[COPY7]] 183 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 184 %ret = call <2 x ptr addrspace(1)> @llvm.amdgcn.raw.ptr.buffer.load.v2p1(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 185 ret <2 x ptr addrspace(1)> %ret 186} 187 188define void @buffer_store_v2p5(<2 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %buf) { 189 ; GFX9-LABEL: name: buffer_store_v2p5 190 ; GFX9: bb.1 (%ir-block.0): 191 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1, $vgpr2, $vgpr3 192 ; GFX9-NEXT: {{ $}} 193 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 194 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 195 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 196 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 197 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 198 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 199 ; GFX9-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 200 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr16 201 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr17 202 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr18 203 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr19 204 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 205 ; GFX9-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 206 ; GFX9-NEXT: BUFFER_STORE_DWORDX4_OFFSET_exact [[REG_SEQUENCE2]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x s64>) into %ir.buf, align 1, addrspace 8) 207 ; GFX9-NEXT: SI_RETURN 208 call void @llvm.amdgcn.raw.ptr.buffer.store.v2p1(<2 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 209 ret void 210} 211 212define <3 x ptr addrspace(5)> @buffer_load_v3p5(ptr addrspace(8) inreg %buf) { 213 ; GFX9-LABEL: name: buffer_load_v3p5 214 ; GFX9: bb.1 (%ir-block.0): 215 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 216 ; GFX9-NEXT: {{ $}} 217 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 218 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 219 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 220 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 221 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 222 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 223 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX3_OFFSET:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x s32>) from %ir.buf, align 1, addrspace 8) 224 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFSET]].sub0 225 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFSET]].sub1 226 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFSET]].sub2 227 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]] 228 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]] 229 ; GFX9-NEXT: $vgpr2 = COPY [[COPY6]] 230 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 231 %ret = call <3 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v3p5(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 232 ret <3 x ptr addrspace(5)> %ret 233} 234 235define void @buffer_store_v3p5(<3 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) { 236 ; GFX9-LABEL: name: buffer_store_v3p5 237 ; GFX9: bb.1 (%ir-block.0): 238 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1, $vgpr2 239 ; GFX9-NEXT: {{ $}} 240 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 241 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 242 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 243 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 244 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr16 245 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr17 246 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr18 247 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr19 248 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 249 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 250 ; GFX9-NEXT: BUFFER_STORE_DWORDX3_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s32>) into %ir.buf, align 1, addrspace 8) 251 ; GFX9-NEXT: SI_RETURN 252 call void @llvm.amdgcn.raw.ptr.buffer.store.v3p5(<3 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 253 ret void 254} 255 256define <4 x ptr addrspace(5)> @buffer_load_v4p5(ptr addrspace(8) inreg %buf) { 257 ; GFX9-LABEL: name: buffer_load_v4p5 258 ; GFX9: bb.1 (%ir-block.0): 259 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19 260 ; GFX9-NEXT: {{ $}} 261 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16 262 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17 263 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 264 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19 265 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 266 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 267 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>) from %ir.buf, align 1, addrspace 8) 268 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub0 269 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub1 270 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub2 271 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub3 272 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]] 273 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]] 274 ; GFX9-NEXT: $vgpr2 = COPY [[COPY6]] 275 ; GFX9-NEXT: $vgpr3 = COPY [[COPY7]] 276 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 277 %ret = call <4 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v4p5(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 278 ret <4 x ptr addrspace(5)> %ret 279} 280 281define void @buffer_store_v4p5(<4 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) { 282 ; GFX9-LABEL: name: buffer_store_v4p5 283 ; GFX9: bb.1 (%ir-block.0): 284 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1, $vgpr2, $vgpr3 285 ; GFX9-NEXT: {{ $}} 286 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 287 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 288 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 289 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 290 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 291 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr16 292 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr17 293 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr18 294 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr19 295 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 296 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 297 ; GFX9-NEXT: BUFFER_STORE_DWORDX4_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x s32>) into %ir.buf, align 1, addrspace 8) 298 ; GFX9-NEXT: SI_RETURN 299 call void @llvm.amdgcn.raw.ptr.buffer.store.v4p5(<4 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0) 300 ret void 301} 302