xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir (revision 8871c3c562690347d75190be758312d1f92a7db4) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3
4---
5name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
6body: |
7  bb.0:
8    liveins: $vgpr0_vgpr1
9
10    ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
11    ; CHECK: liveins: $vgpr0_vgpr1
12    ; CHECK-NEXT: {{  $}}
13    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
14    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
15    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
16    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
17    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
18    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
19    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
20    %1:_(<2 x s16>) = G_TRUNC %0
21    %2:_(<2 x s32>) = G_SEXT %1
22    $vgpr0_vgpr1 = COPY %2
23...
24
25---
26name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
27body: |
28  bb.0:
29    liveins: $vgpr0_vgpr1
30
31    ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
32    ; CHECK: liveins: $vgpr0_vgpr1
33    ; CHECK-NEXT: {{  $}}
34    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
35    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
36    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
37    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
38    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT]], 16
39    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT1]], 16
40    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT_INREG]](s64), [[SEXT_INREG1]](s64)
41    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
42    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
43    %1:_(<2 x s16>) = G_TRUNC %0
44    %2:_(<2 x s64>) = G_SEXT %1
45    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
46...
47
48---
49name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
50body: |
51  bb.0:
52    liveins: $vgpr0_vgpr1
53
54    ; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and
55    ; unable to legalize. This prevents further legalization.
56    ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
57    ; CHECK: liveins: $vgpr0_vgpr1
58    ; CHECK-NEXT: {{  $}}
59    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
60    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
61    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
62    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
63    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
64    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
65    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
66    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
67    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
68    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
69    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
70    ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
71    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
72    %1:_(<2 x s8>) = G_TRUNC %0
73    %2:_(<2 x s16>) = G_SEXT %1
74    $vgpr0 = COPY %2
75...
76
77---
78name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
79body: |
80  bb.0:
81    liveins: $vgpr0_vgpr1_vgpr2
82
83    ; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
84    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
85    ; CHECK-NEXT: {{  $}}
86    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
87    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
88    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
89    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
90    ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
91    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
92    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
93    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
94    %1:_(<3 x s16>) = G_TRUNC %0
95    %2:_(<3 x s32>) = G_SEXT %1
96    $vgpr0_vgpr1_vgpr2 = COPY %2
97...
98