1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5; CHECK-GI: warning: Instruction selection used fallback path for zext_v16i10_v16i16 6 7define i16 @zext_i8_to_i16(i8 %a) { 8; CHECK-LABEL: zext_i8_to_i16: 9; CHECK: // %bb.0: // %entry 10; CHECK-NEXT: and w0, w0, #0xff 11; CHECK-NEXT: ret 12entry: 13 %c = zext i8 %a to i16 14 ret i16 %c 15} 16 17define i32 @zext_i8_to_i32(i8 %a) { 18; CHECK-LABEL: zext_i8_to_i32: 19; CHECK: // %bb.0: // %entry 20; CHECK-NEXT: and w0, w0, #0xff 21; CHECK-NEXT: ret 22entry: 23 %c = zext i8 %a to i32 24 ret i32 %c 25} 26 27define i64 @zext_i8_to_i64(i8 %a) { 28; CHECK-LABEL: zext_i8_to_i64: 29; CHECK: // %bb.0: // %entry 30; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 31; CHECK-NEXT: and x0, x0, #0xff 32; CHECK-NEXT: ret 33entry: 34 %c = zext i8 %a to i64 35 ret i64 %c 36} 37 38define i10 @zext_i8_to_i10(i8 %a) { 39; CHECK-LABEL: zext_i8_to_i10: 40; CHECK: // %bb.0: // %entry 41; CHECK-NEXT: and w0, w0, #0xff 42; CHECK-NEXT: ret 43entry: 44 %c = zext i8 %a to i10 45 ret i10 %c 46} 47 48define i32 @zext_i16_to_i32(i16 %a) { 49; CHECK-LABEL: zext_i16_to_i32: 50; CHECK: // %bb.0: // %entry 51; CHECK-NEXT: and w0, w0, #0xffff 52; CHECK-NEXT: ret 53entry: 54 %c = zext i16 %a to i32 55 ret i32 %c 56} 57 58define i64 @zext_i16_to_i64(i16 %a) { 59; CHECK-LABEL: zext_i16_to_i64: 60; CHECK: // %bb.0: // %entry 61; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 62; CHECK-NEXT: and x0, x0, #0xffff 63; CHECK-NEXT: ret 64entry: 65 %c = zext i16 %a to i64 66 ret i64 %c 67} 68 69define i64 @zext_i32_to_i64(i32 %a) { 70; CHECK-LABEL: zext_i32_to_i64: 71; CHECK: // %bb.0: // %entry 72; CHECK-NEXT: mov w0, w0 73; CHECK-NEXT: ret 74entry: 75 %c = zext i32 %a to i64 76 ret i64 %c 77} 78 79define i16 @zext_i10_to_i16(i10 %a) { 80; CHECK-LABEL: zext_i10_to_i16: 81; CHECK: // %bb.0: // %entry 82; CHECK-NEXT: and w0, w0, #0x3ff 83; CHECK-NEXT: ret 84entry: 85 %c = zext i10 %a to i16 86 ret i16 %c 87} 88 89define i32 @zext_i10_to_i32(i10 %a) { 90; CHECK-LABEL: zext_i10_to_i32: 91; CHECK: // %bb.0: // %entry 92; CHECK-NEXT: and w0, w0, #0x3ff 93; CHECK-NEXT: ret 94entry: 95 %c = zext i10 %a to i32 96 ret i32 %c 97} 98 99define i64 @zext_i10_to_i64(i10 %a) { 100; CHECK-LABEL: zext_i10_to_i64: 101; CHECK: // %bb.0: // %entry 102; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 103; CHECK-NEXT: and x0, x0, #0x3ff 104; CHECK-NEXT: ret 105entry: 106 %c = zext i10 %a to i64 107 ret i64 %c 108} 109 110define <2 x i16> @zext_v2i8_v2i16(<2 x i8> %a) { 111; CHECK-LABEL: zext_v2i8_v2i16: 112; CHECK: // %bb.0: // %entry 113; CHECK-NEXT: movi d1, #0x0000ff000000ff 114; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 115; CHECK-NEXT: ret 116entry: 117 %c = zext <2 x i8> %a to <2 x i16> 118 ret <2 x i16> %c 119} 120 121define <2 x i32> @zext_v2i8_v2i32(<2 x i8> %a) { 122; CHECK-LABEL: zext_v2i8_v2i32: 123; CHECK: // %bb.0: // %entry 124; CHECK-NEXT: movi d1, #0x0000ff000000ff 125; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 126; CHECK-NEXT: ret 127entry: 128 %c = zext <2 x i8> %a to <2 x i32> 129 ret <2 x i32> %c 130} 131 132define <2 x i64> @zext_v2i8_v2i64(<2 x i8> %a) { 133; CHECK-SD-LABEL: zext_v2i8_v2i64: 134; CHECK-SD: // %bb.0: // %entry 135; CHECK-SD-NEXT: movi d1, #0x0000ff000000ff 136; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 137; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 138; CHECK-SD-NEXT: ret 139; 140; CHECK-GI-LABEL: zext_v2i8_v2i64: 141; CHECK-GI: // %bb.0: // %entry 142; CHECK-GI-NEXT: movi v1.2d, #0x000000000000ff 143; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0 144; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 145; CHECK-GI-NEXT: ret 146entry: 147 %c = zext <2 x i8> %a to <2 x i64> 148 ret <2 x i64> %c 149} 150 151define <2 x i32> @zext_v2i16_v2i32(<2 x i16> %a) { 152; CHECK-LABEL: zext_v2i16_v2i32: 153; CHECK: // %bb.0: // %entry 154; CHECK-NEXT: movi d1, #0x00ffff0000ffff 155; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 156; CHECK-NEXT: ret 157entry: 158 %c = zext <2 x i16> %a to <2 x i32> 159 ret <2 x i32> %c 160} 161 162define <2 x i64> @zext_v2i16_v2i64(<2 x i16> %a) { 163; CHECK-SD-LABEL: zext_v2i16_v2i64: 164; CHECK-SD: // %bb.0: // %entry 165; CHECK-SD-NEXT: movi d1, #0x00ffff0000ffff 166; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 167; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 168; CHECK-SD-NEXT: ret 169; 170; CHECK-GI-LABEL: zext_v2i16_v2i64: 171; CHECK-GI: // %bb.0: // %entry 172; CHECK-GI-NEXT: movi v1.2d, #0x0000000000ffff 173; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0 174; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 175; CHECK-GI-NEXT: ret 176entry: 177 %c = zext <2 x i16> %a to <2 x i64> 178 ret <2 x i64> %c 179} 180 181define <2 x i64> @zext_v2i32_v2i64(<2 x i32> %a) { 182; CHECK-LABEL: zext_v2i32_v2i64: 183; CHECK: // %bb.0: // %entry 184; CHECK-NEXT: ushll v0.2d, v0.2s, #0 185; CHECK-NEXT: ret 186entry: 187 %c = zext <2 x i32> %a to <2 x i64> 188 ret <2 x i64> %c 189} 190 191define <2 x i16> @zext_v2i10_v2i16(<2 x i10> %a) { 192; CHECK-LABEL: zext_v2i10_v2i16: 193; CHECK: // %bb.0: // %entry 194; CHECK-NEXT: movi v1.2s, #3, msl #8 195; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 196; CHECK-NEXT: ret 197entry: 198 %c = zext <2 x i10> %a to <2 x i16> 199 ret <2 x i16> %c 200} 201 202define <2 x i32> @zext_v2i10_v2i32(<2 x i10> %a) { 203; CHECK-LABEL: zext_v2i10_v2i32: 204; CHECK: // %bb.0: // %entry 205; CHECK-NEXT: movi v1.2s, #3, msl #8 206; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 207; CHECK-NEXT: ret 208entry: 209 %c = zext <2 x i10> %a to <2 x i32> 210 ret <2 x i32> %c 211} 212 213define <2 x i64> @zext_v2i10_v2i64(<2 x i10> %a) { 214; CHECK-SD-LABEL: zext_v2i10_v2i64: 215; CHECK-SD: // %bb.0: // %entry 216; CHECK-SD-NEXT: movi v1.2s, #3, msl #8 217; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 218; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 219; CHECK-SD-NEXT: ret 220; 221; CHECK-GI-LABEL: zext_v2i10_v2i64: 222; CHECK-GI: // %bb.0: // %entry 223; CHECK-GI-NEXT: adrp x8, .LCPI18_0 224; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0 225; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI18_0] 226; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 227; CHECK-GI-NEXT: ret 228entry: 229 %c = zext <2 x i10> %a to <2 x i64> 230 ret <2 x i64> %c 231} 232 233define <3 x i16> @zext_v3i8_v3i16(<3 x i8> %a) { 234; CHECK-SD-LABEL: zext_v3i8_v3i16: 235; CHECK-SD: // %bb.0: // %entry 236; CHECK-SD-NEXT: fmov s0, w0 237; CHECK-SD-NEXT: mov v0.h[1], w1 238; CHECK-SD-NEXT: mov v0.h[2], w2 239; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8 240; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 241; CHECK-SD-NEXT: ret 242; 243; CHECK-GI-LABEL: zext_v3i8_v3i16: 244; CHECK-GI: // %bb.0: // %entry 245; CHECK-GI-NEXT: and w8, w0, #0xff 246; CHECK-GI-NEXT: and w9, w1, #0xff 247; CHECK-GI-NEXT: fmov s0, w8 248; CHECK-GI-NEXT: and w8, w2, #0xff 249; CHECK-GI-NEXT: mov v0.h[1], w9 250; CHECK-GI-NEXT: mov v0.h[2], w8 251; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 252; CHECK-GI-NEXT: ret 253entry: 254 %c = zext <3 x i8> %a to <3 x i16> 255 ret <3 x i16> %c 256} 257 258define <3 x i32> @zext_v3i8_v3i32(<3 x i8> %a) { 259; CHECK-SD-LABEL: zext_v3i8_v3i32: 260; CHECK-SD: // %bb.0: // %entry 261; CHECK-SD-NEXT: fmov s0, w0 262; CHECK-SD-NEXT: movi v1.2d, #0x0000ff000000ff 263; CHECK-SD-NEXT: mov v0.h[1], w1 264; CHECK-SD-NEXT: mov v0.h[2], w2 265; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 266; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b 267; CHECK-SD-NEXT: ret 268; 269; CHECK-GI-LABEL: zext_v3i8_v3i32: 270; CHECK-GI: // %bb.0: // %entry 271; CHECK-GI-NEXT: and w8, w0, #0xff 272; CHECK-GI-NEXT: mov v0.s[0], w8 273; CHECK-GI-NEXT: and w8, w1, #0xff 274; CHECK-GI-NEXT: mov v0.s[1], w8 275; CHECK-GI-NEXT: and w8, w2, #0xff 276; CHECK-GI-NEXT: mov v0.s[2], w8 277; CHECK-GI-NEXT: ret 278entry: 279 %c = zext <3 x i8> %a to <3 x i32> 280 ret <3 x i32> %c 281} 282 283define <3 x i64> @zext_v3i8_v3i64(<3 x i8> %a) { 284; CHECK-SD-LABEL: zext_v3i8_v3i64: 285; CHECK-SD: // %bb.0: // %entry 286; CHECK-SD-NEXT: fmov s0, w0 287; CHECK-SD-NEXT: movi v1.2d, #0x000000000000ff 288; CHECK-SD-NEXT: fmov s3, w2 289; CHECK-SD-NEXT: movi v2.2d, #0000000000000000 290; CHECK-SD-NEXT: mov v0.s[1], w1 291; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 292; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b 293; CHECK-SD-NEXT: ushll v1.2d, v3.2s, #0 294; CHECK-SD-NEXT: mov v2.b[0], v1.b[0] 295; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 296; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 297; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 298; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2 299; CHECK-SD-NEXT: ret 300; 301; CHECK-GI-LABEL: zext_v3i8_v3i64: 302; CHECK-GI: // %bb.0: // %entry 303; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0 304; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1 305; CHECK-GI-NEXT: // kill: def $w2 killed $w2 def $x2 306; CHECK-GI-NEXT: and x8, x0, #0xff 307; CHECK-GI-NEXT: and x9, x1, #0xff 308; CHECK-GI-NEXT: and x10, x2, #0xff 309; CHECK-GI-NEXT: fmov d0, x8 310; CHECK-GI-NEXT: fmov d1, x9 311; CHECK-GI-NEXT: fmov d2, x10 312; CHECK-GI-NEXT: ret 313entry: 314 %c = zext <3 x i8> %a to <3 x i64> 315 ret <3 x i64> %c 316} 317 318define <3 x i32> @zext_v3i16_v3i32(<3 x i16> %a) { 319; CHECK-SD-LABEL: zext_v3i16_v3i32: 320; CHECK-SD: // %bb.0: // %entry 321; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 322; CHECK-SD-NEXT: ret 323; 324; CHECK-GI-LABEL: zext_v3i16_v3i32: 325; CHECK-GI: // %bb.0: // %entry 326; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 327; CHECK-GI-NEXT: umov w8, v0.h[0] 328; CHECK-GI-NEXT: umov w9, v0.h[1] 329; CHECK-GI-NEXT: mov v1.s[0], w8 330; CHECK-GI-NEXT: umov w8, v0.h[2] 331; CHECK-GI-NEXT: mov v1.s[1], w9 332; CHECK-GI-NEXT: mov v1.s[2], w8 333; CHECK-GI-NEXT: mov v0.16b, v1.16b 334; CHECK-GI-NEXT: ret 335entry: 336 %c = zext <3 x i16> %a to <3 x i32> 337 ret <3 x i32> %c 338} 339 340define <3 x i64> @zext_v3i16_v3i64(<3 x i16> %a) { 341; CHECK-SD-LABEL: zext_v3i16_v3i64: 342; CHECK-SD: // %bb.0: // %entry 343; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0 344; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0 345; CHECK-SD-NEXT: ushll2 v2.2d, v2.4s, #0 346; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2 347; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 348; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 349; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 350; CHECK-SD-NEXT: ret 351; 352; CHECK-GI-LABEL: zext_v3i16_v3i64: 353; CHECK-GI: // %bb.0: // %entry 354; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 355; CHECK-GI-NEXT: umov w8, v0.h[0] 356; CHECK-GI-NEXT: umov w9, v0.h[1] 357; CHECK-GI-NEXT: umov w10, v0.h[2] 358; CHECK-GI-NEXT: fmov d0, x8 359; CHECK-GI-NEXT: fmov d1, x9 360; CHECK-GI-NEXT: fmov d2, x10 361; CHECK-GI-NEXT: ret 362entry: 363 %c = zext <3 x i16> %a to <3 x i64> 364 ret <3 x i64> %c 365} 366 367define <3 x i64> @zext_v3i32_v3i64(<3 x i32> %a) { 368; CHECK-SD-LABEL: zext_v3i32_v3i64: 369; CHECK-SD: // %bb.0: // %entry 370; CHECK-SD-NEXT: ushll v3.2d, v0.2s, #0 371; CHECK-SD-NEXT: ushll2 v2.2d, v0.4s, #0 372; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2 373; CHECK-SD-NEXT: fmov d0, d3 374; CHECK-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8 375; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 376; CHECK-SD-NEXT: ret 377; 378; CHECK-GI-LABEL: zext_v3i32_v3i64: 379; CHECK-GI: // %bb.0: // %entry 380; CHECK-GI-NEXT: mov w8, v0.s[0] 381; CHECK-GI-NEXT: mov w9, v0.s[1] 382; CHECK-GI-NEXT: mov w10, v0.s[2] 383; CHECK-GI-NEXT: fmov d0, x8 384; CHECK-GI-NEXT: fmov d1, x9 385; CHECK-GI-NEXT: fmov d2, x10 386; CHECK-GI-NEXT: ret 387entry: 388 %c = zext <3 x i32> %a to <3 x i64> 389 ret <3 x i64> %c 390} 391 392define <3 x i16> @zext_v3i10_v3i16(<3 x i10> %a) { 393; CHECK-SD-LABEL: zext_v3i10_v3i16: 394; CHECK-SD: // %bb.0: // %entry 395; CHECK-SD-NEXT: fmov s0, w0 396; CHECK-SD-NEXT: mov v0.h[1], w1 397; CHECK-SD-NEXT: mov v0.h[2], w2 398; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8 399; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 400; CHECK-SD-NEXT: ret 401; 402; CHECK-GI-LABEL: zext_v3i10_v3i16: 403; CHECK-GI: // %bb.0: // %entry 404; CHECK-GI-NEXT: and w8, w0, #0x3ff 405; CHECK-GI-NEXT: and w9, w1, #0x3ff 406; CHECK-GI-NEXT: fmov s0, w8 407; CHECK-GI-NEXT: and w8, w2, #0x3ff 408; CHECK-GI-NEXT: mov v0.h[1], w9 409; CHECK-GI-NEXT: mov v0.h[2], w8 410; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 411; CHECK-GI-NEXT: ret 412entry: 413 %c = zext <3 x i10> %a to <3 x i16> 414 ret <3 x i16> %c 415} 416 417define <3 x i32> @zext_v3i10_v3i32(<3 x i10> %a) { 418; CHECK-SD-LABEL: zext_v3i10_v3i32: 419; CHECK-SD: // %bb.0: // %entry 420; CHECK-SD-NEXT: fmov s0, w0 421; CHECK-SD-NEXT: movi v1.4s, #3, msl #8 422; CHECK-SD-NEXT: mov v0.h[1], w1 423; CHECK-SD-NEXT: mov v0.h[2], w2 424; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 425; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b 426; CHECK-SD-NEXT: ret 427; 428; CHECK-GI-LABEL: zext_v3i10_v3i32: 429; CHECK-GI: // %bb.0: // %entry 430; CHECK-GI-NEXT: and w8, w0, #0x3ff 431; CHECK-GI-NEXT: mov v0.s[0], w8 432; CHECK-GI-NEXT: and w8, w1, #0x3ff 433; CHECK-GI-NEXT: mov v0.s[1], w8 434; CHECK-GI-NEXT: and w8, w2, #0x3ff 435; CHECK-GI-NEXT: mov v0.s[2], w8 436; CHECK-GI-NEXT: ret 437entry: 438 %c = zext <3 x i10> %a to <3 x i32> 439 ret <3 x i32> %c 440} 441 442define <3 x i64> @zext_v3i10_v3i64(<3 x i10> %a) { 443; CHECK-SD-LABEL: zext_v3i10_v3i64: 444; CHECK-SD: // %bb.0: // %entry 445; CHECK-SD-NEXT: fmov s0, w0 446; CHECK-SD-NEXT: fmov s1, w2 447; CHECK-SD-NEXT: mov w8, #1023 // =0x3ff 448; CHECK-SD-NEXT: dup v2.2d, x8 449; CHECK-SD-NEXT: mov v0.s[1], w1 450; CHECK-SD-NEXT: ushll v3.2d, v1.2s, #0 451; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 452; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b 453; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b 454; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 455; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 456; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 457; CHECK-SD-NEXT: ret 458; 459; CHECK-GI-LABEL: zext_v3i10_v3i64: 460; CHECK-GI: // %bb.0: // %entry 461; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0 462; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1 463; CHECK-GI-NEXT: // kill: def $w2 killed $w2 def $x2 464; CHECK-GI-NEXT: and x8, x0, #0x3ff 465; CHECK-GI-NEXT: and x9, x1, #0x3ff 466; CHECK-GI-NEXT: and x10, x2, #0x3ff 467; CHECK-GI-NEXT: fmov d0, x8 468; CHECK-GI-NEXT: fmov d1, x9 469; CHECK-GI-NEXT: fmov d2, x10 470; CHECK-GI-NEXT: ret 471entry: 472 %c = zext <3 x i10> %a to <3 x i64> 473 ret <3 x i64> %c 474} 475 476define <4 x i16> @zext_v4i8_v4i16(<4 x i8> %a) { 477; CHECK-SD-LABEL: zext_v4i8_v4i16: 478; CHECK-SD: // %bb.0: // %entry 479; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8 480; CHECK-SD-NEXT: ret 481; 482; CHECK-GI-LABEL: zext_v4i8_v4i16: 483; CHECK-GI: // %bb.0: // %entry 484; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff 485; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 486; CHECK-GI-NEXT: ret 487entry: 488 %c = zext <4 x i8> %a to <4 x i16> 489 ret <4 x i16> %c 490} 491 492define <4 x i32> @zext_v4i8_v4i32(<4 x i8> %a) { 493; CHECK-SD-LABEL: zext_v4i8_v4i32: 494; CHECK-SD: // %bb.0: // %entry 495; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8 496; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 497; CHECK-SD-NEXT: ret 498; 499; CHECK-GI-LABEL: zext_v4i8_v4i32: 500; CHECK-GI: // %bb.0: // %entry 501; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff 502; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0 503; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 504; CHECK-GI-NEXT: ret 505entry: 506 %c = zext <4 x i8> %a to <4 x i32> 507 ret <4 x i32> %c 508} 509 510define <4 x i64> @zext_v4i8_v4i64(<4 x i8> %a) { 511; CHECK-SD-LABEL: zext_v4i8_v4i64: 512; CHECK-SD: // %bb.0: // %entry 513; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8 514; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 515; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0 516; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 517; CHECK-SD-NEXT: ret 518; 519; CHECK-GI-LABEL: zext_v4i8_v4i64: 520; CHECK-GI: // %bb.0: // %entry 521; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0 522; CHECK-GI-NEXT: movi v1.2d, #0x000000000000ff 523; CHECK-GI-NEXT: ushll v2.2d, v0.2s, #0 524; CHECK-GI-NEXT: ushll2 v3.2d, v0.4s, #0 525; CHECK-GI-NEXT: and v0.16b, v2.16b, v1.16b 526; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b 527; CHECK-GI-NEXT: ret 528entry: 529 %c = zext <4 x i8> %a to <4 x i64> 530 ret <4 x i64> %c 531} 532 533define <4 x i32> @zext_v4i16_v4i32(<4 x i16> %a) { 534; CHECK-LABEL: zext_v4i16_v4i32: 535; CHECK: // %bb.0: // %entry 536; CHECK-NEXT: ushll v0.4s, v0.4h, #0 537; CHECK-NEXT: ret 538entry: 539 %c = zext <4 x i16> %a to <4 x i32> 540 ret <4 x i32> %c 541} 542 543define <4 x i64> @zext_v4i16_v4i64(<4 x i16> %a) { 544; CHECK-SD-LABEL: zext_v4i16_v4i64: 545; CHECK-SD: // %bb.0: // %entry 546; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 547; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0 548; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 549; CHECK-SD-NEXT: ret 550; 551; CHECK-GI-LABEL: zext_v4i16_v4i64: 552; CHECK-GI: // %bb.0: // %entry 553; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0 554; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0 555; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0 556; CHECK-GI-NEXT: ret 557entry: 558 %c = zext <4 x i16> %a to <4 x i64> 559 ret <4 x i64> %c 560} 561 562define <4 x i64> @zext_v4i32_v4i64(<4 x i32> %a) { 563; CHECK-SD-LABEL: zext_v4i32_v4i64: 564; CHECK-SD: // %bb.0: // %entry 565; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0 566; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 567; CHECK-SD-NEXT: ret 568; 569; CHECK-GI-LABEL: zext_v4i32_v4i64: 570; CHECK-GI: // %bb.0: // %entry 571; CHECK-GI-NEXT: ushll v2.2d, v0.2s, #0 572; CHECK-GI-NEXT: ushll2 v1.2d, v0.4s, #0 573; CHECK-GI-NEXT: mov v0.16b, v2.16b 574; CHECK-GI-NEXT: ret 575entry: 576 %c = zext <4 x i32> %a to <4 x i64> 577 ret <4 x i64> %c 578} 579 580define <4 x i16> @zext_v4i10_v4i16(<4 x i10> %a) { 581; CHECK-SD-LABEL: zext_v4i10_v4i16: 582; CHECK-SD: // %bb.0: // %entry 583; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8 584; CHECK-SD-NEXT: ret 585; 586; CHECK-GI-LABEL: zext_v4i10_v4i16: 587; CHECK-GI: // %bb.0: // %entry 588; CHECK-GI-NEXT: mvni v1.4h, #252, lsl #8 589; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 590; CHECK-GI-NEXT: ret 591entry: 592 %c = zext <4 x i10> %a to <4 x i16> 593 ret <4 x i16> %c 594} 595 596define <4 x i32> @zext_v4i10_v4i32(<4 x i10> %a) { 597; CHECK-SD-LABEL: zext_v4i10_v4i32: 598; CHECK-SD: // %bb.0: // %entry 599; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8 600; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 601; CHECK-SD-NEXT: ret 602; 603; CHECK-GI-LABEL: zext_v4i10_v4i32: 604; CHECK-GI: // %bb.0: // %entry 605; CHECK-GI-NEXT: movi v1.4s, #3, msl #8 606; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0 607; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 608; CHECK-GI-NEXT: ret 609entry: 610 %c = zext <4 x i10> %a to <4 x i32> 611 ret <4 x i32> %c 612} 613 614define <4 x i64> @zext_v4i10_v4i64(<4 x i10> %a) { 615; CHECK-SD-LABEL: zext_v4i10_v4i64: 616; CHECK-SD: // %bb.0: // %entry 617; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8 618; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 619; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0 620; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 621; CHECK-SD-NEXT: ret 622; 623; CHECK-GI-LABEL: zext_v4i10_v4i64: 624; CHECK-GI: // %bb.0: // %entry 625; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0 626; CHECK-GI-NEXT: adrp x8, .LCPI36_0 627; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI36_0] 628; CHECK-GI-NEXT: ushll v1.2d, v0.2s, #0 629; CHECK-GI-NEXT: ushll2 v2.2d, v0.4s, #0 630; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b 631; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b 632; CHECK-GI-NEXT: ret 633entry: 634 %c = zext <4 x i10> %a to <4 x i64> 635 ret <4 x i64> %c 636} 637 638define <8 x i16> @zext_v8i8_v8i16(<8 x i8> %a) { 639; CHECK-LABEL: zext_v8i8_v8i16: 640; CHECK: // %bb.0: // %entry 641; CHECK-NEXT: ushll v0.8h, v0.8b, #0 642; CHECK-NEXT: ret 643entry: 644 %c = zext <8 x i8> %a to <8 x i16> 645 ret <8 x i16> %c 646} 647 648define <8 x i32> @zext_v8i8_v8i32(<8 x i8> %a) { 649; CHECK-SD-LABEL: zext_v8i8_v8i32: 650; CHECK-SD: // %bb.0: // %entry 651; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0 652; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0 653; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 654; CHECK-SD-NEXT: ret 655; 656; CHECK-GI-LABEL: zext_v8i8_v8i32: 657; CHECK-GI: // %bb.0: // %entry 658; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0 659; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0 660; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0 661; CHECK-GI-NEXT: ret 662entry: 663 %c = zext <8 x i8> %a to <8 x i32> 664 ret <8 x i32> %c 665} 666 667define <8 x i64> @zext_v8i8_v8i64(<8 x i8> %a) { 668; CHECK-SD-LABEL: zext_v8i8_v8i64: 669; CHECK-SD: // %bb.0: // %entry 670; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0 671; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0 672; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0 673; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0 674; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0 675; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0 676; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0 677; CHECK-SD-NEXT: ret 678; 679; CHECK-GI-LABEL: zext_v8i8_v8i64: 680; CHECK-GI: // %bb.0: // %entry 681; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0 682; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0 683; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0 684; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0 685; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0 686; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0 687; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0 688; CHECK-GI-NEXT: ret 689entry: 690 %c = zext <8 x i8> %a to <8 x i64> 691 ret <8 x i64> %c 692} 693 694define <8 x i32> @zext_v8i16_v8i32(<8 x i16> %a) { 695; CHECK-SD-LABEL: zext_v8i16_v8i32: 696; CHECK-SD: // %bb.0: // %entry 697; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0 698; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 699; CHECK-SD-NEXT: ret 700; 701; CHECK-GI-LABEL: zext_v8i16_v8i32: 702; CHECK-GI: // %bb.0: // %entry 703; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0 704; CHECK-GI-NEXT: ushll2 v1.4s, v0.8h, #0 705; CHECK-GI-NEXT: mov v0.16b, v2.16b 706; CHECK-GI-NEXT: ret 707entry: 708 %c = zext <8 x i16> %a to <8 x i32> 709 ret <8 x i32> %c 710} 711 712define <8 x i64> @zext_v8i16_v8i64(<8 x i16> %a) { 713; CHECK-SD-LABEL: zext_v8i16_v8i64: 714; CHECK-SD: // %bb.0: // %entry 715; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0 716; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0 717; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0 718; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0 719; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0 720; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0 721; CHECK-SD-NEXT: ret 722; 723; CHECK-GI-LABEL: zext_v8i16_v8i64: 724; CHECK-GI: // %bb.0: // %entry 725; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0 726; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0 727; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0 728; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0 729; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0 730; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0 731; CHECK-GI-NEXT: ret 732entry: 733 %c = zext <8 x i16> %a to <8 x i64> 734 ret <8 x i64> %c 735} 736 737define <8 x i64> @zext_v8i32_v8i64(<8 x i32> %a) { 738; CHECK-SD-LABEL: zext_v8i32_v8i64: 739; CHECK-SD: // %bb.0: // %entry 740; CHECK-SD-NEXT: ushll v5.2d, v0.2s, #0 741; CHECK-SD-NEXT: ushll2 v4.2d, v0.4s, #0 742; CHECK-SD-NEXT: ushll2 v3.2d, v1.4s, #0 743; CHECK-SD-NEXT: ushll v2.2d, v1.2s, #0 744; CHECK-SD-NEXT: mov v0.16b, v5.16b 745; CHECK-SD-NEXT: mov v1.16b, v4.16b 746; CHECK-SD-NEXT: ret 747; 748; CHECK-GI-LABEL: zext_v8i32_v8i64: 749; CHECK-GI: // %bb.0: // %entry 750; CHECK-GI-NEXT: ushll v4.2d, v0.2s, #0 751; CHECK-GI-NEXT: ushll2 v5.2d, v0.4s, #0 752; CHECK-GI-NEXT: ushll v2.2d, v1.2s, #0 753; CHECK-GI-NEXT: ushll2 v3.2d, v1.4s, #0 754; CHECK-GI-NEXT: mov v0.16b, v4.16b 755; CHECK-GI-NEXT: mov v1.16b, v5.16b 756; CHECK-GI-NEXT: ret 757entry: 758 %c = zext <8 x i32> %a to <8 x i64> 759 ret <8 x i64> %c 760} 761 762define <8 x i16> @zext_v8i10_v8i16(<8 x i10> %a) { 763; CHECK-SD-LABEL: zext_v8i10_v8i16: 764; CHECK-SD: // %bb.0: // %entry 765; CHECK-SD-NEXT: bic v0.8h, #252, lsl #8 766; CHECK-SD-NEXT: ret 767; 768; CHECK-GI-LABEL: zext_v8i10_v8i16: 769; CHECK-GI: // %bb.0: // %entry 770; CHECK-GI-NEXT: mvni v1.8h, #252, lsl #8 771; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 772; CHECK-GI-NEXT: ret 773entry: 774 %c = zext <8 x i10> %a to <8 x i16> 775 ret <8 x i16> %c 776} 777 778define <8 x i32> @zext_v8i10_v8i32(<8 x i10> %a) { 779; CHECK-SD-LABEL: zext_v8i10_v8i32: 780; CHECK-SD: // %bb.0: // %entry 781; CHECK-SD-NEXT: bic v0.8h, #252, lsl #8 782; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0 783; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 784; CHECK-SD-NEXT: ret 785; 786; CHECK-GI-LABEL: zext_v8i10_v8i32: 787; CHECK-GI: // %bb.0: // %entry 788; CHECK-GI-NEXT: movi v1.4s, #3, msl #8 789; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0 790; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0 791; CHECK-GI-NEXT: and v0.16b, v2.16b, v1.16b 792; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b 793; CHECK-GI-NEXT: ret 794entry: 795 %c = zext <8 x i10> %a to <8 x i32> 796 ret <8 x i32> %c 797} 798 799define <8 x i64> @zext_v8i10_v8i64(<8 x i10> %a) { 800; CHECK-SD-LABEL: zext_v8i10_v8i64: 801; CHECK-SD: // %bb.0: // %entry 802; CHECK-SD-NEXT: bic v0.8h, #252, lsl #8 803; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0 804; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0 805; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0 806; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0 807; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0 808; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0 809; CHECK-SD-NEXT: ret 810; 811; CHECK-GI-LABEL: zext_v8i10_v8i64: 812; CHECK-GI: // %bb.0: // %entry 813; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0 814; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0 815; CHECK-GI-NEXT: adrp x8, .LCPI45_0 816; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI45_0] 817; CHECK-GI-NEXT: ushll v2.2d, v1.2s, #0 818; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0 819; CHECK-GI-NEXT: ushll v4.2d, v0.2s, #0 820; CHECK-GI-NEXT: ushll2 v5.2d, v0.4s, #0 821; CHECK-GI-NEXT: and v0.16b, v2.16b, v3.16b 822; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 823; CHECK-GI-NEXT: and v2.16b, v4.16b, v3.16b 824; CHECK-GI-NEXT: and v3.16b, v5.16b, v3.16b 825; CHECK-GI-NEXT: ret 826entry: 827 %c = zext <8 x i10> %a to <8 x i64> 828 ret <8 x i64> %c 829} 830 831define <16 x i16> @zext_v16i8_v16i16(<16 x i8> %a) { 832; CHECK-SD-LABEL: zext_v16i8_v16i16: 833; CHECK-SD: // %bb.0: // %entry 834; CHECK-SD-NEXT: ushll2 v1.8h, v0.16b, #0 835; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0 836; CHECK-SD-NEXT: ret 837; 838; CHECK-GI-LABEL: zext_v16i8_v16i16: 839; CHECK-GI: // %bb.0: // %entry 840; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0 841; CHECK-GI-NEXT: ushll2 v1.8h, v0.16b, #0 842; CHECK-GI-NEXT: mov v0.16b, v2.16b 843; CHECK-GI-NEXT: ret 844entry: 845 %c = zext <16 x i8> %a to <16 x i16> 846 ret <16 x i16> %c 847} 848 849define <16 x i32> @zext_v16i8_v16i32(<16 x i8> %a) { 850; CHECK-SD-LABEL: zext_v16i8_v16i32: 851; CHECK-SD: // %bb.0: // %entry 852; CHECK-SD-NEXT: ushll v1.8h, v0.8b, #0 853; CHECK-SD-NEXT: ushll2 v2.8h, v0.16b, #0 854; CHECK-SD-NEXT: ushll v0.4s, v1.4h, #0 855; CHECK-SD-NEXT: ushll2 v3.4s, v2.8h, #0 856; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0 857; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0 858; CHECK-SD-NEXT: ret 859; 860; CHECK-GI-LABEL: zext_v16i8_v16i32: 861; CHECK-GI: // %bb.0: // %entry 862; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0 863; CHECK-GI-NEXT: ushll2 v3.8h, v0.16b, #0 864; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0 865; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0 866; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0 867; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0 868; CHECK-GI-NEXT: ret 869entry: 870 %c = zext <16 x i8> %a to <16 x i32> 871 ret <16 x i32> %c 872} 873 874define <16 x i64> @zext_v16i8_v16i64(<16 x i8> %a) { 875; CHECK-SD-LABEL: zext_v16i8_v16i64: 876; CHECK-SD: // %bb.0: // %entry 877; CHECK-SD-NEXT: ushll v1.8h, v0.8b, #0 878; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0 879; CHECK-SD-NEXT: ushll v2.4s, v1.4h, #0 880; CHECK-SD-NEXT: ushll2 v4.4s, v1.8h, #0 881; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0 882; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #0 883; CHECK-SD-NEXT: ushll2 v1.2d, v2.4s, #0 884; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0 885; CHECK-SD-NEXT: ushll2 v3.2d, v4.4s, #0 886; CHECK-SD-NEXT: ushll v2.2d, v4.2s, #0 887; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0 888; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0 889; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0 890; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0 891; CHECK-SD-NEXT: ret 892; 893; CHECK-GI-LABEL: zext_v16i8_v16i64: 894; CHECK-GI: // %bb.0: // %entry 895; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0 896; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0 897; CHECK-GI-NEXT: ushll v2.4s, v1.4h, #0 898; CHECK-GI-NEXT: ushll2 v3.4s, v1.8h, #0 899; CHECK-GI-NEXT: ushll v5.4s, v0.4h, #0 900; CHECK-GI-NEXT: ushll2 v7.4s, v0.8h, #0 901; CHECK-GI-NEXT: ushll v0.2d, v2.2s, #0 902; CHECK-GI-NEXT: ushll2 v1.2d, v2.4s, #0 903; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0 904; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0 905; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #0 906; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #0 907; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #0 908; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0 909; CHECK-GI-NEXT: ret 910entry: 911 %c = zext <16 x i8> %a to <16 x i64> 912 ret <16 x i64> %c 913} 914 915define <16 x i32> @zext_v16i16_v16i32(<16 x i16> %a) { 916; CHECK-SD-LABEL: zext_v16i16_v16i32: 917; CHECK-SD: // %bb.0: // %entry 918; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0 919; CHECK-SD-NEXT: ushll2 v4.4s, v0.8h, #0 920; CHECK-SD-NEXT: ushll2 v3.4s, v1.8h, #0 921; CHECK-SD-NEXT: ushll v2.4s, v1.4h, #0 922; CHECK-SD-NEXT: mov v0.16b, v5.16b 923; CHECK-SD-NEXT: mov v1.16b, v4.16b 924; CHECK-SD-NEXT: ret 925; 926; CHECK-GI-LABEL: zext_v16i16_v16i32: 927; CHECK-GI: // %bb.0: // %entry 928; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0 929; CHECK-GI-NEXT: ushll2 v5.4s, v0.8h, #0 930; CHECK-GI-NEXT: ushll v2.4s, v1.4h, #0 931; CHECK-GI-NEXT: ushll2 v3.4s, v1.8h, #0 932; CHECK-GI-NEXT: mov v0.16b, v4.16b 933; CHECK-GI-NEXT: mov v1.16b, v5.16b 934; CHECK-GI-NEXT: ret 935entry: 936 %c = zext <16 x i16> %a to <16 x i32> 937 ret <16 x i32> %c 938} 939 940define <16 x i64> @zext_v16i16_v16i64(<16 x i16> %a) { 941; CHECK-SD-LABEL: zext_v16i16_v16i64: 942; CHECK-SD: // %bb.0: // %entry 943; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0 944; CHECK-SD-NEXT: ushll2 v4.4s, v0.8h, #0 945; CHECK-SD-NEXT: ushll v5.4s, v1.4h, #0 946; CHECK-SD-NEXT: ushll2 v6.4s, v1.8h, #0 947; CHECK-SD-NEXT: ushll2 v1.2d, v2.4s, #0 948; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0 949; CHECK-SD-NEXT: ushll2 v3.2d, v4.4s, #0 950; CHECK-SD-NEXT: ushll v2.2d, v4.2s, #0 951; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0 952; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0 953; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0 954; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0 955; CHECK-SD-NEXT: ret 956; 957; CHECK-GI-LABEL: zext_v16i16_v16i64: 958; CHECK-GI: // %bb.0: // %entry 959; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0 960; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0 961; CHECK-GI-NEXT: ushll v5.4s, v1.4h, #0 962; CHECK-GI-NEXT: ushll2 v7.4s, v1.8h, #0 963; CHECK-GI-NEXT: ushll v0.2d, v2.2s, #0 964; CHECK-GI-NEXT: ushll2 v1.2d, v2.4s, #0 965; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0 966; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0 967; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #0 968; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #0 969; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #0 970; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0 971; CHECK-GI-NEXT: ret 972entry: 973 %c = zext <16 x i16> %a to <16 x i64> 974 ret <16 x i64> %c 975} 976 977define <16 x i64> @zext_v16i32_v16i64(<16 x i32> %a) { 978; CHECK-SD-LABEL: zext_v16i32_v16i64: 979; CHECK-SD: // %bb.0: // %entry 980; CHECK-SD-NEXT: ushll2 v17.2d, v0.4s, #0 981; CHECK-SD-NEXT: ushll2 v16.2d, v1.4s, #0 982; CHECK-SD-NEXT: ushll v18.2d, v1.2s, #0 983; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0 984; CHECK-SD-NEXT: ushll v4.2d, v2.2s, #0 985; CHECK-SD-NEXT: ushll2 v5.2d, v2.4s, #0 986; CHECK-SD-NEXT: ushll2 v7.2d, v3.4s, #0 987; CHECK-SD-NEXT: ushll v6.2d, v3.2s, #0 988; CHECK-SD-NEXT: mov v1.16b, v17.16b 989; CHECK-SD-NEXT: mov v2.16b, v18.16b 990; CHECK-SD-NEXT: mov v3.16b, v16.16b 991; CHECK-SD-NEXT: ret 992; 993; CHECK-GI-LABEL: zext_v16i32_v16i64: 994; CHECK-GI: // %bb.0: // %entry 995; CHECK-GI-NEXT: ushll v16.2d, v0.2s, #0 996; CHECK-GI-NEXT: ushll2 v17.2d, v0.4s, #0 997; CHECK-GI-NEXT: ushll v18.2d, v1.2s, #0 998; CHECK-GI-NEXT: ushll2 v19.2d, v1.4s, #0 999; CHECK-GI-NEXT: ushll v4.2d, v2.2s, #0 1000; CHECK-GI-NEXT: ushll2 v5.2d, v2.4s, #0 1001; CHECK-GI-NEXT: ushll v6.2d, v3.2s, #0 1002; CHECK-GI-NEXT: ushll2 v7.2d, v3.4s, #0 1003; CHECK-GI-NEXT: mov v0.16b, v16.16b 1004; CHECK-GI-NEXT: mov v1.16b, v17.16b 1005; CHECK-GI-NEXT: mov v2.16b, v18.16b 1006; CHECK-GI-NEXT: mov v3.16b, v19.16b 1007; CHECK-GI-NEXT: ret 1008entry: 1009 %c = zext <16 x i32> %a to <16 x i64> 1010 ret <16 x i64> %c 1011} 1012 1013define <16 x i16> @zext_v16i10_v16i16(<16 x i10> %a) { 1014; CHECK-LABEL: zext_v16i10_v16i16: 1015; CHECK: // %bb.0: // %entry 1016; CHECK-NEXT: ldr w8, [sp] 1017; CHECK-NEXT: fmov s0, w0 1018; CHECK-NEXT: ldr w9, [sp, #8] 1019; CHECK-NEXT: fmov s1, w8 1020; CHECK-NEXT: ldr w8, [sp, #16] 1021; CHECK-NEXT: mov v0.h[1], w1 1022; CHECK-NEXT: mov v1.h[1], w9 1023; CHECK-NEXT: mov v0.h[2], w2 1024; CHECK-NEXT: mov v1.h[2], w8 1025; CHECK-NEXT: ldr w8, [sp, #24] 1026; CHECK-NEXT: mov v0.h[3], w3 1027; CHECK-NEXT: mov v1.h[3], w8 1028; CHECK-NEXT: ldr w8, [sp, #32] 1029; CHECK-NEXT: mov v0.h[4], w4 1030; CHECK-NEXT: mov v1.h[4], w8 1031; CHECK-NEXT: ldr w8, [sp, #40] 1032; CHECK-NEXT: mov v0.h[5], w5 1033; CHECK-NEXT: mov v1.h[5], w8 1034; CHECK-NEXT: ldr w8, [sp, #48] 1035; CHECK-NEXT: mov v0.h[6], w6 1036; CHECK-NEXT: mov v1.h[6], w8 1037; CHECK-NEXT: ldr w8, [sp, #56] 1038; CHECK-NEXT: mov v0.h[7], w7 1039; CHECK-NEXT: mov v1.h[7], w8 1040; CHECK-NEXT: bic v0.8h, #252, lsl #8 1041; CHECK-NEXT: bic v1.8h, #252, lsl #8 1042; CHECK-NEXT: ret 1043entry: 1044 %c = zext <16 x i10> %a to <16 x i16> 1045 ret <16 x i16> %c 1046} 1047 1048define <16 x i32> @zext_v16i10_v16i32(<16 x i10> %a) { 1049; CHECK-SD-LABEL: zext_v16i10_v16i32: 1050; CHECK-SD: // %bb.0: // %entry 1051; CHECK-SD-NEXT: ldr w8, [sp, #32] 1052; CHECK-SD-NEXT: ldr w9, [sp] 1053; CHECK-SD-NEXT: fmov s0, w0 1054; CHECK-SD-NEXT: fmov s1, w4 1055; CHECK-SD-NEXT: ldr w10, [sp, #40] 1056; CHECK-SD-NEXT: ldr w11, [sp, #8] 1057; CHECK-SD-NEXT: fmov s2, w9 1058; CHECK-SD-NEXT: fmov s3, w8 1059; CHECK-SD-NEXT: ldr w8, [sp, #48] 1060; CHECK-SD-NEXT: mov v0.h[1], w1 1061; CHECK-SD-NEXT: ldr w9, [sp, #16] 1062; CHECK-SD-NEXT: movi v4.4s, #3, msl #8 1063; CHECK-SD-NEXT: mov v1.h[1], w5 1064; CHECK-SD-NEXT: mov v2.h[1], w11 1065; CHECK-SD-NEXT: mov v3.h[1], w10 1066; CHECK-SD-NEXT: mov v0.h[2], w2 1067; CHECK-SD-NEXT: mov v1.h[2], w6 1068; CHECK-SD-NEXT: mov v2.h[2], w9 1069; CHECK-SD-NEXT: mov v3.h[2], w8 1070; CHECK-SD-NEXT: ldr w8, [sp, #56] 1071; CHECK-SD-NEXT: ldr w9, [sp, #24] 1072; CHECK-SD-NEXT: mov v0.h[3], w3 1073; CHECK-SD-NEXT: mov v1.h[3], w7 1074; CHECK-SD-NEXT: mov v2.h[3], w9 1075; CHECK-SD-NEXT: mov v3.h[3], w8 1076; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0 1077; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0 1078; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0 1079; CHECK-SD-NEXT: ushll v3.4s, v3.4h, #0 1080; CHECK-SD-NEXT: and v0.16b, v0.16b, v4.16b 1081; CHECK-SD-NEXT: and v1.16b, v1.16b, v4.16b 1082; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b 1083; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b 1084; CHECK-SD-NEXT: ret 1085; 1086; CHECK-GI-LABEL: zext_v16i10_v16i32: 1087; CHECK-GI: // %bb.0: // %entry 1088; CHECK-GI-NEXT: ldr w8, [sp] 1089; CHECK-GI-NEXT: ldr w9, [sp, #32] 1090; CHECK-GI-NEXT: fmov s0, w0 1091; CHECK-GI-NEXT: fmov s1, w4 1092; CHECK-GI-NEXT: ldr w10, [sp, #8] 1093; CHECK-GI-NEXT: ldr w11, [sp, #40] 1094; CHECK-GI-NEXT: fmov s2, w8 1095; CHECK-GI-NEXT: fmov s3, w9 1096; CHECK-GI-NEXT: ldr w8, [sp, #16] 1097; CHECK-GI-NEXT: mov v0.h[1], w1 1098; CHECK-GI-NEXT: ldr w9, [sp, #48] 1099; CHECK-GI-NEXT: movi v4.4s, #3, msl #8 1100; CHECK-GI-NEXT: mov v1.h[1], w5 1101; CHECK-GI-NEXT: mov v2.h[1], w10 1102; CHECK-GI-NEXT: mov v3.h[1], w11 1103; CHECK-GI-NEXT: mov v0.h[2], w2 1104; CHECK-GI-NEXT: mov v1.h[2], w6 1105; CHECK-GI-NEXT: mov v2.h[2], w8 1106; CHECK-GI-NEXT: mov v3.h[2], w9 1107; CHECK-GI-NEXT: ldr w8, [sp, #24] 1108; CHECK-GI-NEXT: ldr w9, [sp, #56] 1109; CHECK-GI-NEXT: mov v0.h[3], w3 1110; CHECK-GI-NEXT: mov v1.h[3], w7 1111; CHECK-GI-NEXT: mov v2.h[3], w8 1112; CHECK-GI-NEXT: mov v3.h[3], w9 1113; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0 1114; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0 1115; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0 1116; CHECK-GI-NEXT: ushll v3.4s, v3.4h, #0 1117; CHECK-GI-NEXT: and v0.16b, v0.16b, v4.16b 1118; CHECK-GI-NEXT: and v1.16b, v1.16b, v4.16b 1119; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b 1120; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b 1121; CHECK-GI-NEXT: ret 1122entry: 1123 %c = zext <16 x i10> %a to <16 x i32> 1124 ret <16 x i32> %c 1125} 1126 1127define <16 x i64> @zext_v16i10_v16i64(<16 x i10> %a) { 1128; CHECK-SD-LABEL: zext_v16i10_v16i64: 1129; CHECK-SD: // %bb.0: // %entry 1130; CHECK-SD-NEXT: fmov s0, w2 1131; CHECK-SD-NEXT: fmov s1, w0 1132; CHECK-SD-NEXT: ldr s2, [sp] 1133; CHECK-SD-NEXT: fmov s3, w4 1134; CHECK-SD-NEXT: fmov s4, w6 1135; CHECK-SD-NEXT: add x9, sp, #8 1136; CHECK-SD-NEXT: ldr s5, [sp, #16] 1137; CHECK-SD-NEXT: ldr s6, [sp, #32] 1138; CHECK-SD-NEXT: ldr s7, [sp, #48] 1139; CHECK-SD-NEXT: mov v1.s[1], w1 1140; CHECK-SD-NEXT: mov v0.s[1], w3 1141; CHECK-SD-NEXT: ld1 { v2.s }[1], [x9] 1142; CHECK-SD-NEXT: mov v3.s[1], w5 1143; CHECK-SD-NEXT: mov v4.s[1], w7 1144; CHECK-SD-NEXT: add x9, sp, #24 1145; CHECK-SD-NEXT: add x10, sp, #40 1146; CHECK-SD-NEXT: add x11, sp, #56 1147; CHECK-SD-NEXT: ld1 { v5.s }[1], [x9] 1148; CHECK-SD-NEXT: ld1 { v6.s }[1], [x10] 1149; CHECK-SD-NEXT: ld1 { v7.s }[1], [x11] 1150; CHECK-SD-NEXT: mov w8, #1023 // =0x3ff 1151; CHECK-SD-NEXT: ushll v1.2d, v1.2s, #0 1152; CHECK-SD-NEXT: dup v16.2d, x8 1153; CHECK-SD-NEXT: ushll v17.2d, v0.2s, #0 1154; CHECK-SD-NEXT: ushll v3.2d, v3.2s, #0 1155; CHECK-SD-NEXT: ushll v4.2d, v4.2s, #0 1156; CHECK-SD-NEXT: ushll v18.2d, v2.2s, #0 1157; CHECK-SD-NEXT: ushll v5.2d, v5.2s, #0 1158; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0 1159; CHECK-SD-NEXT: ushll v7.2d, v7.2s, #0 1160; CHECK-SD-NEXT: and v0.16b, v1.16b, v16.16b 1161; CHECK-SD-NEXT: and v1.16b, v17.16b, v16.16b 1162; CHECK-SD-NEXT: and v2.16b, v3.16b, v16.16b 1163; CHECK-SD-NEXT: and v3.16b, v4.16b, v16.16b 1164; CHECK-SD-NEXT: and v4.16b, v18.16b, v16.16b 1165; CHECK-SD-NEXT: and v5.16b, v5.16b, v16.16b 1166; CHECK-SD-NEXT: and v6.16b, v6.16b, v16.16b 1167; CHECK-SD-NEXT: and v7.16b, v7.16b, v16.16b 1168; CHECK-SD-NEXT: ret 1169; 1170; CHECK-GI-LABEL: zext_v16i10_v16i64: 1171; CHECK-GI: // %bb.0: // %entry 1172; CHECK-GI-NEXT: mov v0.s[0], w0 1173; CHECK-GI-NEXT: mov v1.s[0], w2 1174; CHECK-GI-NEXT: ldr s3, [sp] 1175; CHECK-GI-NEXT: mov v2.s[0], w4 1176; CHECK-GI-NEXT: mov v5.s[0], w6 1177; CHECK-GI-NEXT: ldr s4, [sp, #8] 1178; CHECK-GI-NEXT: ldr s6, [sp, #16] 1179; CHECK-GI-NEXT: ldr s7, [sp, #24] 1180; CHECK-GI-NEXT: ldr s16, [sp, #32] 1181; CHECK-GI-NEXT: ldr s17, [sp, #40] 1182; CHECK-GI-NEXT: ldr s18, [sp, #48] 1183; CHECK-GI-NEXT: ldr s19, [sp, #56] 1184; CHECK-GI-NEXT: mov v0.s[1], w1 1185; CHECK-GI-NEXT: mov v1.s[1], w3 1186; CHECK-GI-NEXT: mov v3.s[1], v4.s[0] 1187; CHECK-GI-NEXT: mov v2.s[1], w5 1188; CHECK-GI-NEXT: mov v5.s[1], w7 1189; CHECK-GI-NEXT: mov v6.s[1], v7.s[0] 1190; CHECK-GI-NEXT: mov v16.s[1], v17.s[0] 1191; CHECK-GI-NEXT: mov v18.s[1], v19.s[0] 1192; CHECK-GI-NEXT: adrp x8, .LCPI54_0 1193; CHECK-GI-NEXT: ldr q7, [x8, :lo12:.LCPI54_0] 1194; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0 1195; CHECK-GI-NEXT: ushll v1.2d, v1.2s, #0 1196; CHECK-GI-NEXT: ushll v2.2d, v2.2s, #0 1197; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #0 1198; CHECK-GI-NEXT: ushll v5.2d, v3.2s, #0 1199; CHECK-GI-NEXT: ushll v6.2d, v6.2s, #0 1200; CHECK-GI-NEXT: ushll v16.2d, v16.2s, #0 1201; CHECK-GI-NEXT: ushll v17.2d, v18.2s, #0 1202; CHECK-GI-NEXT: and v0.16b, v0.16b, v7.16b 1203; CHECK-GI-NEXT: and v1.16b, v1.16b, v7.16b 1204; CHECK-GI-NEXT: and v2.16b, v2.16b, v7.16b 1205; CHECK-GI-NEXT: and v3.16b, v4.16b, v7.16b 1206; CHECK-GI-NEXT: and v4.16b, v5.16b, v7.16b 1207; CHECK-GI-NEXT: and v5.16b, v6.16b, v7.16b 1208; CHECK-GI-NEXT: and v6.16b, v16.16b, v7.16b 1209; CHECK-GI-NEXT: and v7.16b, v17.16b, v7.16b 1210; CHECK-GI-NEXT: ret 1211entry: 1212 %c = zext <16 x i10> %a to <16 x i64> 1213 ret <16 x i64> %c 1214} 1215