xref: /llvm-project/llvm/test/CodeGen/AArch64/zext-logic-shift-load.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb)
1; RUN: llc -mtriple=aarch64-linux-gnu < %s -o - | FileCheck %s
2
3define i32 @test1(ptr %p) {
4; CHECK:       ldrb
5; CHECK-NEXT:  ubfx
6; CHECK-NEXT:  ret
7
8  %1 = load i8, ptr %p
9  %2 = lshr i8 %1, 1
10  %3 = and i8 %2, 1
11  %4 = zext i8 %3 to i32
12  ret i32 %4
13}
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