xref: /llvm-project/llvm/test/CodeGen/AArch64/zeroing-forms-ext.ll (revision 5d6d982df61d16b6d498e6d59dd91c059679d3d8) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mattr=+sve    < %s | FileCheck %s
3; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2
4
5; RUN: llc -mattr=+sme    -force-streaming < %s | FileCheck %s
6; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2
7
8target triple = "aarch64-linux"
9
10define <vscale x 8 x i16> @test_svextb_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) {
11; CHECK-LABEL: test_svextb_s16_x_1:
12; CHECK:       // %bb.0: // %entry
13; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
14; CHECK-NEXT:    ret
15;
16; CHECK-2p2-LABEL: test_svextb_s16_x_1:
17; CHECK-2p2:       // %bb.0: // %entry
18; CHECK-2p2-NEXT:    sxtb z0.h, p0/z, z0.h
19; CHECK-2p2-NEXT:    ret
20entry:
21  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
22  ret <vscale x 8 x i16> %0
23}
24
25define <vscale x 8 x i16> @test_svextb_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
26; CHECK-LABEL: test_svextb_s16_x_2:
27; CHECK:       // %bb.0: // %entry
28; CHECK-NEXT:    movprfx z0, z1
29; CHECK-NEXT:    sxtb z0.h, p0/m, z1.h
30; CHECK-NEXT:    ret
31;
32; CHECK-2p2-LABEL: test_svextb_s16_x_2:
33; CHECK-2p2:       // %bb.0: // %entry
34; CHECK-2p2-NEXT:    sxtb z0.h, p0/z, z1.h
35; CHECK-2p2-NEXT:    ret
36entry:
37  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
38  ret <vscale x 8 x i16> %0
39}
40
41define <vscale x 8 x i16> @test_svextb_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
42; CHECK-LABEL: test_svextb_s16_z:
43; CHECK:       // %bb.0: // %entry
44; CHECK-NEXT:    mov z0.h, #0 // =0x0
45; CHECK-NEXT:    sxtb z0.h, p0/m, z1.h
46; CHECK-NEXT:    ret
47;
48; CHECK-2p2-LABEL: test_svextb_s16_z:
49; CHECK-2p2:       // %bb.0: // %entry
50; CHECK-2p2-NEXT:    sxtb z0.h, p0/z, z1.h
51; CHECK-2p2-NEXT:    ret
52entry:
53  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
54  ret <vscale x 8 x i16> %0
55}
56
57define <vscale x 4 x i32> @test_svextb_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
58; CHECK-LABEL: test_svextb_s32_x_1:
59; CHECK:       // %bb.0: // %entry
60; CHECK-NEXT:    sxtb z0.s, p0/m, z0.s
61; CHECK-NEXT:    ret
62;
63; CHECK-2p2-LABEL: test_svextb_s32_x_1:
64; CHECK-2p2:       // %bb.0: // %entry
65; CHECK-2p2-NEXT:    sxtb z0.s, p0/z, z0.s
66; CHECK-2p2-NEXT:    ret
67entry:
68  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
69  ret <vscale x 4 x i32> %0
70}
71
72define <vscale x 4 x i32> @test_svextb_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
73; CHECK-LABEL: test_svextb_s32_x_2:
74; CHECK:       // %bb.0: // %entry
75; CHECK-NEXT:    movprfx z0, z1
76; CHECK-NEXT:    sxtb z0.s, p0/m, z1.s
77; CHECK-NEXT:    ret
78;
79; CHECK-2p2-LABEL: test_svextb_s32_x_2:
80; CHECK-2p2:       // %bb.0: // %entry
81; CHECK-2p2-NEXT:    sxtb z0.s, p0/z, z1.s
82; CHECK-2p2-NEXT:    ret
83entry:
84  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
85  ret <vscale x 4 x i32> %0
86}
87
88define <vscale x 4 x i32> @test_svextb_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
89; CHECK-LABEL: test_svextb_s32_z:
90; CHECK:       // %bb.0: // %entry
91; CHECK-NEXT:    mov z0.s, #0 // =0x0
92; CHECK-NEXT:    sxtb z0.s, p0/m, z1.s
93; CHECK-NEXT:    ret
94;
95; CHECK-2p2-LABEL: test_svextb_s32_z:
96; CHECK-2p2:       // %bb.0: // %entry
97; CHECK-2p2-NEXT:    sxtb z0.s, p0/z, z1.s
98; CHECK-2p2-NEXT:    ret
99entry:
100  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
101  ret <vscale x 4 x i32> %0
102}
103
104define <vscale x 2 x i64> @test_svextb_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
105; CHECK-LABEL: test_svextb_s64_x_1:
106; CHECK:       // %bb.0: // %entry
107; CHECK-NEXT:    sxtb z0.d, p0/m, z0.d
108; CHECK-NEXT:    ret
109;
110; CHECK-2p2-LABEL: test_svextb_s64_x_1:
111; CHECK-2p2:       // %bb.0: // %entry
112; CHECK-2p2-NEXT:    sxtb z0.d, p0/z, z0.d
113; CHECK-2p2-NEXT:    ret
114entry:
115  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
116  ret <vscale x 2 x i64> %0
117}
118
119define <vscale x 2 x i64> @test_svextb_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
120; CHECK-LABEL: test_svextb_s64_x_2:
121; CHECK:       // %bb.0: // %entry
122; CHECK-NEXT:    movprfx z0, z1
123; CHECK-NEXT:    sxtb z0.d, p0/m, z1.d
124; CHECK-NEXT:    ret
125;
126; CHECK-2p2-LABEL: test_svextb_s64_x_2:
127; CHECK-2p2:       // %bb.0: // %entry
128; CHECK-2p2-NEXT:    sxtb z0.d, p0/z, z1.d
129; CHECK-2p2-NEXT:    ret
130entry:
131  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
132  ret <vscale x 2 x i64> %0
133}
134
135define <vscale x 2 x i64> @test_svextb_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
136; CHECK-LABEL: test_svextb_s64_z:
137; CHECK:       // %bb.0: // %entry
138; CHECK-NEXT:    mov z0.d, #0 // =0x0
139; CHECK-NEXT:    sxtb z0.d, p0/m, z1.d
140; CHECK-NEXT:    ret
141;
142; CHECK-2p2-LABEL: test_svextb_s64_z:
143; CHECK-2p2:       // %bb.0: // %entry
144; CHECK-2p2-NEXT:    sxtb z0.d, p0/z, z1.d
145; CHECK-2p2-NEXT:    ret
146entry:
147  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
148  ret <vscale x 2 x i64> %0
149}
150
151define <vscale x 8 x i16> @test_svextb_u16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) {
152; CHECK-LABEL: test_svextb_u16_x_1:
153; CHECK:       // %bb.0: // %entry
154; CHECK-NEXT:    uxtb z0.h, p0/m, z0.h
155; CHECK-NEXT:    ret
156;
157; CHECK-2p2-LABEL: test_svextb_u16_x_1:
158; CHECK-2p2:       // %bb.0: // %entry
159; CHECK-2p2-NEXT:    uxtb z0.h, p0/z, z0.h
160; CHECK-2p2-NEXT:    ret
161entry:
162  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
163  ret <vscale x 8 x i16> %0
164}
165
166define <vscale x 8 x i16> @test_svextb_u16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
167; CHECK-LABEL: test_svextb_u16_x_2:
168; CHECK:       // %bb.0: // %entry
169; CHECK-NEXT:    movprfx z0, z1
170; CHECK-NEXT:    uxtb z0.h, p0/m, z1.h
171; CHECK-NEXT:    ret
172;
173; CHECK-2p2-LABEL: test_svextb_u16_x_2:
174; CHECK-2p2:       // %bb.0: // %entry
175; CHECK-2p2-NEXT:    uxtb z0.h, p0/z, z1.h
176; CHECK-2p2-NEXT:    ret
177entry:
178  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
179  ret <vscale x 8 x i16> %0
180}
181
182define <vscale x 8 x i16> @test_svextb_u16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
183; CHECK-LABEL: test_svextb_u16_z:
184; CHECK:       // %bb.0: // %entry
185; CHECK-NEXT:    mov z0.h, #0 // =0x0
186; CHECK-NEXT:    uxtb z0.h, p0/m, z1.h
187; CHECK-NEXT:    ret
188;
189; CHECK-2p2-LABEL: test_svextb_u16_z:
190; CHECK-2p2:       // %bb.0: // %entry
191; CHECK-2p2-NEXT:    uxtb z0.h, p0/z, z1.h
192; CHECK-2p2-NEXT:    ret
193entry:
194  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
195  ret <vscale x 8 x i16> %0
196}
197
198define <vscale x 4 x i32> @test_svextb_u32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
199; CHECK-LABEL: test_svextb_u32_x_1:
200; CHECK:       // %bb.0: // %entry
201; CHECK-NEXT:    uxtb z0.s, p0/m, z0.s
202; CHECK-NEXT:    ret
203;
204; CHECK-2p2-LABEL: test_svextb_u32_x_1:
205; CHECK-2p2:       // %bb.0: // %entry
206; CHECK-2p2-NEXT:    uxtb z0.s, p0/z, z0.s
207; CHECK-2p2-NEXT:    ret
208entry:
209  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
210  ret <vscale x 4 x i32> %0
211}
212
213define <vscale x 4 x i32> @test_svextb_u32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
214; CHECK-LABEL: test_svextb_u32_x_2:
215; CHECK:       // %bb.0: // %entry
216; CHECK-NEXT:    movprfx z0, z1
217; CHECK-NEXT:    uxtb z0.s, p0/m, z1.s
218; CHECK-NEXT:    ret
219;
220; CHECK-2p2-LABEL: test_svextb_u32_x_2:
221; CHECK-2p2:       // %bb.0: // %entry
222; CHECK-2p2-NEXT:    uxtb z0.s, p0/z, z1.s
223; CHECK-2p2-NEXT:    ret
224entry:
225  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
226  ret <vscale x 4 x i32> %0
227}
228
229define <vscale x 4 x i32> @test_svextb_u32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
230; CHECK-LABEL: test_svextb_u32_z:
231; CHECK:       // %bb.0: // %entry
232; CHECK-NEXT:    mov z0.s, #0 // =0x0
233; CHECK-NEXT:    uxtb z0.s, p0/m, z1.s
234; CHECK-NEXT:    ret
235;
236; CHECK-2p2-LABEL: test_svextb_u32_z:
237; CHECK-2p2:       // %bb.0: // %entry
238; CHECK-2p2-NEXT:    uxtb z0.s, p0/z, z1.s
239; CHECK-2p2-NEXT:    ret
240entry:
241  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
242  ret <vscale x 4 x i32> %0
243}
244
245define <vscale x 2 x i64> @test_svextb_u64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
246; CHECK-LABEL: test_svextb_u64_x_1:
247; CHECK:       // %bb.0: // %entry
248; CHECK-NEXT:    uxtb z0.d, p0/m, z0.d
249; CHECK-NEXT:    ret
250;
251; CHECK-2p2-LABEL: test_svextb_u64_x_1:
252; CHECK-2p2:       // %bb.0: // %entry
253; CHECK-2p2-NEXT:    uxtb z0.d, p0/z, z0.d
254; CHECK-2p2-NEXT:    ret
255entry:
256  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
257  ret <vscale x 2 x i64> %0
258}
259
260define <vscale x 2 x i64> @test_svextb_u64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
261; CHECK-LABEL: test_svextb_u64_x_2:
262; CHECK:       // %bb.0: // %entry
263; CHECK-NEXT:    movprfx z0, z1
264; CHECK-NEXT:    uxtb z0.d, p0/m, z1.d
265; CHECK-NEXT:    ret
266;
267; CHECK-2p2-LABEL: test_svextb_u64_x_2:
268; CHECK-2p2:       // %bb.0: // %entry
269; CHECK-2p2-NEXT:    uxtb z0.d, p0/z, z1.d
270; CHECK-2p2-NEXT:    ret
271entry:
272  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
273  ret <vscale x 2 x i64> %0
274}
275
276define <vscale x 2 x i64> @test_svextb_u64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
277; CHECK-LABEL: test_svextb_u64_z:
278; CHECK:       // %bb.0: // %entry
279; CHECK-NEXT:    mov z0.d, #0 // =0x0
280; CHECK-NEXT:    uxtb z0.d, p0/m, z1.d
281; CHECK-NEXT:    ret
282;
283; CHECK-2p2-LABEL: test_svextb_u64_z:
284; CHECK-2p2:       // %bb.0: // %entry
285; CHECK-2p2-NEXT:    uxtb z0.d, p0/z, z1.d
286; CHECK-2p2-NEXT:    ret
287entry:
288  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
289  ret <vscale x 2 x i64> %0
290}
291
292define <vscale x 4 x i32> @test_svexth_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
293; CHECK-LABEL: test_svexth_s32_x_1:
294; CHECK:       // %bb.0: // %entry
295; CHECK-NEXT:    sxth z0.s, p0/m, z0.s
296; CHECK-NEXT:    ret
297;
298; CHECK-2p2-LABEL: test_svexth_s32_x_1:
299; CHECK-2p2:       // %bb.0: // %entry
300; CHECK-2p2-NEXT:    sxth z0.s, p0/z, z0.s
301; CHECK-2p2-NEXT:    ret
302entry:
303  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
304  ret <vscale x 4 x i32> %0
305}
306
307define <vscale x 4 x i32> @test_svexth_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
308; CHECK-LABEL: test_svexth_s32_x_2:
309; CHECK:       // %bb.0: // %entry
310; CHECK-NEXT:    movprfx z0, z1
311; CHECK-NEXT:    sxth z0.s, p0/m, z1.s
312; CHECK-NEXT:    ret
313;
314; CHECK-2p2-LABEL: test_svexth_s32_x_2:
315; CHECK-2p2:       // %bb.0: // %entry
316; CHECK-2p2-NEXT:    sxth z0.s, p0/z, z1.s
317; CHECK-2p2-NEXT:    ret
318entry:
319  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
320  ret <vscale x 4 x i32> %0
321}
322
323define <vscale x 4 x i32> @test_svexth_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
324; CHECK-LABEL: test_svexth_s32_z:
325; CHECK:       // %bb.0: // %entry
326; CHECK-NEXT:    mov z0.s, #0 // =0x0
327; CHECK-NEXT:    sxth z0.s, p0/m, z1.s
328; CHECK-NEXT:    ret
329;
330; CHECK-2p2-LABEL: test_svexth_s32_z:
331; CHECK-2p2:       // %bb.0: // %entry
332; CHECK-2p2-NEXT:    sxth z0.s, p0/z, z1.s
333; CHECK-2p2-NEXT:    ret
334entry:
335  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
336  ret <vscale x 4 x i32> %0
337}
338
339define <vscale x 2 x i64> @test_svexth_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
340; CHECK-LABEL: test_svexth_s64_x_1:
341; CHECK:       // %bb.0: // %entry
342; CHECK-NEXT:    sxth z0.d, p0/m, z0.d
343; CHECK-NEXT:    ret
344;
345; CHECK-2p2-LABEL: test_svexth_s64_x_1:
346; CHECK-2p2:       // %bb.0: // %entry
347; CHECK-2p2-NEXT:    sxth z0.d, p0/z, z0.d
348; CHECK-2p2-NEXT:    ret
349entry:
350  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
351  ret <vscale x 2 x i64> %0
352}
353
354define <vscale x 2 x i64> @test_svexth_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
355; CHECK-LABEL: test_svexth_s64_x_2:
356; CHECK:       // %bb.0: // %entry
357; CHECK-NEXT:    movprfx z0, z1
358; CHECK-NEXT:    sxth z0.d, p0/m, z1.d
359; CHECK-NEXT:    ret
360;
361; CHECK-2p2-LABEL: test_svexth_s64_x_2:
362; CHECK-2p2:       // %bb.0: // %entry
363; CHECK-2p2-NEXT:    sxth z0.d, p0/z, z1.d
364; CHECK-2p2-NEXT:    ret
365entry:
366  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
367  ret <vscale x 2 x i64> %0
368}
369
370define <vscale x 2 x i64> @test_svexth_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
371; CHECK-LABEL: test_svexth_s64_z:
372; CHECK:       // %bb.0: // %entry
373; CHECK-NEXT:    mov z0.d, #0 // =0x0
374; CHECK-NEXT:    sxth z0.d, p0/m, z1.d
375; CHECK-NEXT:    ret
376;
377; CHECK-2p2-LABEL: test_svexth_s64_z:
378; CHECK-2p2:       // %bb.0: // %entry
379; CHECK-2p2-NEXT:    sxth z0.d, p0/z, z1.d
380; CHECK-2p2-NEXT:    ret
381entry:
382  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
383  ret <vscale x 2 x i64> %0
384}
385
386define <vscale x 4 x i32> @test_svexth_u32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
387; CHECK-LABEL: test_svexth_u32_x_1:
388; CHECK:       // %bb.0: // %entry
389; CHECK-NEXT:    uxth z0.s, p0/m, z0.s
390; CHECK-NEXT:    ret
391;
392; CHECK-2p2-LABEL: test_svexth_u32_x_1:
393; CHECK-2p2:       // %bb.0: // %entry
394; CHECK-2p2-NEXT:    uxth z0.s, p0/z, z0.s
395; CHECK-2p2-NEXT:    ret
396entry:
397  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
398  ret <vscale x 4 x i32> %0
399}
400
401define <vscale x 4 x i32> @test_svexth_u32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
402; CHECK-LABEL: test_svexth_u32_x_2:
403; CHECK:       // %bb.0: // %entry
404; CHECK-NEXT:    movprfx z0, z1
405; CHECK-NEXT:    uxth z0.s, p0/m, z1.s
406; CHECK-NEXT:    ret
407;
408; CHECK-2p2-LABEL: test_svexth_u32_x_2:
409; CHECK-2p2:       // %bb.0: // %entry
410; CHECK-2p2-NEXT:    uxth z0.s, p0/z, z1.s
411; CHECK-2p2-NEXT:    ret
412entry:
413  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
414  ret <vscale x 4 x i32> %0
415}
416
417define <vscale x 4 x i32> @test_svexth_u32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
418; CHECK-LABEL: test_svexth_u32_z:
419; CHECK:       // %bb.0: // %entry
420; CHECK-NEXT:    mov z0.s, #0 // =0x0
421; CHECK-NEXT:    uxth z0.s, p0/m, z1.s
422; CHECK-NEXT:    ret
423;
424; CHECK-2p2-LABEL: test_svexth_u32_z:
425; CHECK-2p2:       // %bb.0: // %entry
426; CHECK-2p2-NEXT:    uxth z0.s, p0/z, z1.s
427; CHECK-2p2-NEXT:    ret
428entry:
429  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
430  ret <vscale x 4 x i32> %0
431}
432
433define <vscale x 2 x i64> @test_svexth_u64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
434; CHECK-LABEL: test_svexth_u64_x_1:
435; CHECK:       // %bb.0: // %entry
436; CHECK-NEXT:    uxth z0.d, p0/m, z0.d
437; CHECK-NEXT:    ret
438;
439; CHECK-2p2-LABEL: test_svexth_u64_x_1:
440; CHECK-2p2:       // %bb.0: // %entry
441; CHECK-2p2-NEXT:    uxth z0.d, p0/z, z0.d
442; CHECK-2p2-NEXT:    ret
443entry:
444  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
445  ret <vscale x 2 x i64> %0
446}
447
448define <vscale x 2 x i64> @test_svexth_u64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
449; CHECK-LABEL: test_svexth_u64_x_2:
450; CHECK:       // %bb.0: // %entry
451; CHECK-NEXT:    movprfx z0, z1
452; CHECK-NEXT:    uxth z0.d, p0/m, z1.d
453; CHECK-NEXT:    ret
454;
455; CHECK-2p2-LABEL: test_svexth_u64_x_2:
456; CHECK-2p2:       // %bb.0: // %entry
457; CHECK-2p2-NEXT:    uxth z0.d, p0/z, z1.d
458; CHECK-2p2-NEXT:    ret
459entry:
460  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
461  ret <vscale x 2 x i64> %0
462}
463
464define <vscale x 2 x i64> @test_svexth_u64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
465; CHECK-LABEL: test_svexth_u64_z:
466; CHECK:       // %bb.0: // %entry
467; CHECK-NEXT:    mov z0.d, #0 // =0x0
468; CHECK-NEXT:    uxth z0.d, p0/m, z1.d
469; CHECK-NEXT:    ret
470;
471; CHECK-2p2-LABEL: test_svexth_u64_z:
472; CHECK-2p2:       // %bb.0: // %entry
473; CHECK-2p2-NEXT:    uxth z0.d, p0/z, z1.d
474; CHECK-2p2-NEXT:    ret
475entry:
476  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
477  ret <vscale x 2 x i64> %0
478}
479
480define <vscale x 2 x i64> @test_svextw_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
481; CHECK-LABEL: test_svextw_s64_x_1:
482; CHECK:       // %bb.0: // %entry
483; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
484; CHECK-NEXT:    ret
485;
486; CHECK-2p2-LABEL: test_svextw_s64_x_1:
487; CHECK-2p2:       // %bb.0: // %entry
488; CHECK-2p2-NEXT:    sxtw z0.d, p0/z, z0.d
489; CHECK-2p2-NEXT:    ret
490entry:
491  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
492  ret <vscale x 2 x i64> %0
493}
494
495define <vscale x 2 x i64> @test_svextw_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
496; CHECK-LABEL: test_svextw_s64_x_2:
497; CHECK:       // %bb.0: // %entry
498; CHECK-NEXT:    movprfx z0, z1
499; CHECK-NEXT:    sxtw z0.d, p0/m, z1.d
500; CHECK-NEXT:    ret
501;
502; CHECK-2p2-LABEL: test_svextw_s64_x_2:
503; CHECK-2p2:       // %bb.0: // %entry
504; CHECK-2p2-NEXT:    sxtw z0.d, p0/z, z1.d
505; CHECK-2p2-NEXT:    ret
506entry:
507  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
508  ret <vscale x 2 x i64> %0
509}
510
511define <vscale x 2 x i64> @test_svextw_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
512; CHECK-LABEL: test_svextw_s64_z:
513; CHECK:       // %bb.0: // %entry
514; CHECK-NEXT:    mov z0.d, #0 // =0x0
515; CHECK-NEXT:    sxtw z0.d, p0/m, z1.d
516; CHECK-NEXT:    ret
517;
518; CHECK-2p2-LABEL: test_svextw_s64_z:
519; CHECK-2p2:       // %bb.0: // %entry
520; CHECK-2p2-NEXT:    sxtw z0.d, p0/z, z1.d
521; CHECK-2p2-NEXT:    ret
522entry:
523  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
524  ret <vscale x 2 x i64> %0
525}
526
527define <vscale x 2 x i64> @test_svextw_u64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
528; CHECK-LABEL: test_svextw_u64_x_1:
529; CHECK:       // %bb.0: // %entry
530; CHECK-NEXT:    uxtw z0.d, p0/m, z0.d
531; CHECK-NEXT:    ret
532;
533; CHECK-2p2-LABEL: test_svextw_u64_x_1:
534; CHECK-2p2:       // %bb.0: // %entry
535; CHECK-2p2-NEXT:    uxtw z0.d, p0/z, z0.d
536; CHECK-2p2-NEXT:    ret
537entry:
538  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
539  ret <vscale x 2 x i64> %0
540}
541
542define <vscale x 2 x i64> @test_svextw_u64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
543; CHECK-LABEL: test_svextw_u64_x_2:
544; CHECK:       // %bb.0: // %entry
545; CHECK-NEXT:    movprfx z0, z1
546; CHECK-NEXT:    uxtw z0.d, p0/m, z1.d
547; CHECK-NEXT:    ret
548;
549; CHECK-2p2-LABEL: test_svextw_u64_x_2:
550; CHECK-2p2:       // %bb.0: // %entry
551; CHECK-2p2-NEXT:    uxtw z0.d, p0/z, z1.d
552; CHECK-2p2-NEXT:    ret
553entry:
554  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
555  ret <vscale x 2 x i64> %0
556}
557
558define <vscale x 2 x i64> @test_svextw_u64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
559; CHECK-LABEL: test_svextw_u64_z:
560; CHECK:       // %bb.0: // %entry
561; CHECK-NEXT:    mov z0.d, #0 // =0x0
562; CHECK-NEXT:    uxtw z0.d, p0/m, z1.d
563; CHECK-NEXT:    ret
564;
565; CHECK-2p2-LABEL: test_svextw_u64_z:
566; CHECK-2p2:       // %bb.0: // %entry
567; CHECK-2p2-NEXT:    uxtw z0.d, p0/z, z1.d
568; CHECK-2p2-NEXT:    ret
569entry:
570  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
571  ret <vscale x 2 x i64> %0
572}
573
574define <vscale x 8 x i16> @test_svsxtb_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) {
575; CHECK-LABEL: test_svsxtb_nxv8i16_ptrue_u:
576; CHECK:       // %bb.0: // %entry
577; CHECK-NEXT:    ptrue p0.h
578; CHECK-NEXT:    movprfx z0, z1
579; CHECK-NEXT:    sxtb z0.h, p0/m, z1.h
580; CHECK-NEXT:    ret
581;
582; CHECK-2p2-LABEL: test_svsxtb_nxv8i16_ptrue_u:
583; CHECK-2p2:       // %bb.0: // %entry
584; CHECK-2p2-NEXT:    ptrue p0.h
585; CHECK-2p2-NEXT:    sxtb z0.h, p0/z, z1.h
586; CHECK-2p2-NEXT:    ret
587entry:
588  %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
589  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
590  ret <vscale x 8 x i16> %0
591}
592
593define <vscale x 8 x i16> @test_svsxtb_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
594; CHECK-LABEL: test_svsxtb_nxv8i16_ptrue:
595; CHECK:       // %bb.0: // %entry
596; CHECK-NEXT:    ptrue p0.h
597; CHECK-NEXT:    movprfx z0, z2
598; CHECK-NEXT:    sxtb z0.h, p0/m, z2.h
599; CHECK-NEXT:    ret
600;
601; CHECK-2p2-LABEL: test_svsxtb_nxv8i16_ptrue:
602; CHECK-2p2:       // %bb.0: // %entry
603; CHECK-2p2-NEXT:    ptrue p0.h
604; CHECK-2p2-NEXT:    sxtb z0.h, p0/z, z2.h
605; CHECK-2p2-NEXT:    ret
606entry:
607  %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
608  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y)
609  ret <vscale x 8 x i16> %0
610}
611
612define <vscale x 4 x i32> @test_svsxtb_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) {
613; CHECK-LABEL: test_svsxtb_nxv4i32_ptrue_u:
614; CHECK:       // %bb.0: // %entry
615; CHECK-NEXT:    ptrue p0.s
616; CHECK-NEXT:    movprfx z0, z1
617; CHECK-NEXT:    sxtb z0.s, p0/m, z1.s
618; CHECK-NEXT:    ret
619;
620; CHECK-2p2-LABEL: test_svsxtb_nxv4i32_ptrue_u:
621; CHECK-2p2:       // %bb.0: // %entry
622; CHECK-2p2-NEXT:    ptrue p0.s
623; CHECK-2p2-NEXT:    sxtb z0.s, p0/z, z1.s
624; CHECK-2p2-NEXT:    ret
625entry:
626  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
627  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
628  ret <vscale x 4 x i32> %0
629}
630
631define <vscale x 4 x i32> @test_svsxtb_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
632; CHECK-LABEL: test_svsxtb_nxv4i32_ptrue:
633; CHECK:       // %bb.0: // %entry
634; CHECK-NEXT:    ptrue p0.s
635; CHECK-NEXT:    movprfx z0, z2
636; CHECK-NEXT:    sxtb z0.s, p0/m, z2.s
637; CHECK-NEXT:    ret
638;
639; CHECK-2p2-LABEL: test_svsxtb_nxv4i32_ptrue:
640; CHECK-2p2:       // %bb.0: // %entry
641; CHECK-2p2-NEXT:    ptrue p0.s
642; CHECK-2p2-NEXT:    sxtb z0.s, p0/z, z2.s
643; CHECK-2p2-NEXT:    ret
644entry:
645  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
646  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y)
647  ret <vscale x 4 x i32> %0
648}
649
650define <vscale x 2 x i64> @test_svsxtb_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) {
651; CHECK-LABEL: test_svsxtb_nxv2i64_ptrue_u:
652; CHECK:       // %bb.0: // %entry
653; CHECK-NEXT:    ptrue p0.d
654; CHECK-NEXT:    movprfx z0, z1
655; CHECK-NEXT:    sxtb z0.d, p0/m, z1.d
656; CHECK-NEXT:    ret
657;
658; CHECK-2p2-LABEL: test_svsxtb_nxv2i64_ptrue_u:
659; CHECK-2p2:       // %bb.0: // %entry
660; CHECK-2p2-NEXT:    ptrue p0.d
661; CHECK-2p2-NEXT:    sxtb z0.d, p0/z, z1.d
662; CHECK-2p2-NEXT:    ret
663entry:
664  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
665  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
666  ret <vscale x 2 x i64> %0
667}
668
669define <vscale x 2 x i64> @test_svsxtb_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
670; CHECK-LABEL: test_svsxtb_nxv2i64_ptrue:
671; CHECK:       // %bb.0: // %entry
672; CHECK-NEXT:    ptrue p0.d
673; CHECK-NEXT:    movprfx z0, z2
674; CHECK-NEXT:    sxtb z0.d, p0/m, z2.d
675; CHECK-NEXT:    ret
676;
677; CHECK-2p2-LABEL: test_svsxtb_nxv2i64_ptrue:
678; CHECK-2p2:       // %bb.0: // %entry
679; CHECK-2p2-NEXT:    ptrue p0.d
680; CHECK-2p2-NEXT:    sxtb z0.d, p0/z, z2.d
681; CHECK-2p2-NEXT:    ret
682entry:
683  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
684  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y)
685  ret <vscale x 2 x i64> %0
686}
687
688define <vscale x 8 x i16> @test_svuxtb_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) {
689; CHECK-LABEL: test_svuxtb_nxv8i16_ptrue_u:
690; CHECK:       // %bb.0: // %entry
691; CHECK-NEXT:    ptrue p0.h
692; CHECK-NEXT:    movprfx z0, z1
693; CHECK-NEXT:    uxtb z0.h, p0/m, z1.h
694; CHECK-NEXT:    ret
695;
696; CHECK-2p2-LABEL: test_svuxtb_nxv8i16_ptrue_u:
697; CHECK-2p2:       // %bb.0: // %entry
698; CHECK-2p2-NEXT:    ptrue p0.h
699; CHECK-2p2-NEXT:    uxtb z0.h, p0/z, z1.h
700; CHECK-2p2-NEXT:    ret
701entry:
702  %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
703  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
704  ret <vscale x 8 x i16> %0
705}
706
707define <vscale x 8 x i16> @test_svuxtb_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
708; CHECK-LABEL: test_svuxtb_nxv8i16_ptrue:
709; CHECK:       // %bb.0: // %entry
710; CHECK-NEXT:    ptrue p0.h
711; CHECK-NEXT:    movprfx z0, z2
712; CHECK-NEXT:    uxtb z0.h, p0/m, z2.h
713; CHECK-NEXT:    ret
714;
715; CHECK-2p2-LABEL: test_svuxtb_nxv8i16_ptrue:
716; CHECK-2p2:       // %bb.0: // %entry
717; CHECK-2p2-NEXT:    ptrue p0.h
718; CHECK-2p2-NEXT:    uxtb z0.h, p0/z, z2.h
719; CHECK-2p2-NEXT:    ret
720entry:
721  %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
722  %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y)
723  ret <vscale x 8 x i16> %0
724}
725
726define <vscale x 4 x i32> @test_svuxtb_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) {
727; CHECK-LABEL: test_svuxtb_nxv4i32_ptrue_u:
728; CHECK:       // %bb.0: // %entry
729; CHECK-NEXT:    ptrue p0.s
730; CHECK-NEXT:    movprfx z0, z1
731; CHECK-NEXT:    uxtb z0.s, p0/m, z1.s
732; CHECK-NEXT:    ret
733;
734; CHECK-2p2-LABEL: test_svuxtb_nxv4i32_ptrue_u:
735; CHECK-2p2:       // %bb.0: // %entry
736; CHECK-2p2-NEXT:    ptrue p0.s
737; CHECK-2p2-NEXT:    uxtb z0.s, p0/z, z1.s
738; CHECK-2p2-NEXT:    ret
739entry:
740  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
741  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
742  ret <vscale x 4 x i32> %0
743}
744
745define <vscale x 4 x i32> @test_svuxtb_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
746; CHECK-LABEL: test_svuxtb_nxv4i32_ptrue:
747; CHECK:       // %bb.0: // %entry
748; CHECK-NEXT:    ptrue p0.s
749; CHECK-NEXT:    movprfx z0, z2
750; CHECK-NEXT:    uxtb z0.s, p0/m, z2.s
751; CHECK-NEXT:    ret
752;
753; CHECK-2p2-LABEL: test_svuxtb_nxv4i32_ptrue:
754; CHECK-2p2:       // %bb.0: // %entry
755; CHECK-2p2-NEXT:    ptrue p0.s
756; CHECK-2p2-NEXT:    uxtb z0.s, p0/z, z2.s
757; CHECK-2p2-NEXT:    ret
758entry:
759  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
760  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y)
761  ret <vscale x 4 x i32> %0
762}
763
764define <vscale x 2 x i64> @test_svuxtb_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) {
765; CHECK-LABEL: test_svuxtb_nxv2i64_ptrue_u:
766; CHECK:       // %bb.0: // %entry
767; CHECK-NEXT:    ptrue p0.d
768; CHECK-NEXT:    movprfx z0, z1
769; CHECK-NEXT:    uxtb z0.d, p0/m, z1.d
770; CHECK-NEXT:    ret
771;
772; CHECK-2p2-LABEL: test_svuxtb_nxv2i64_ptrue_u:
773; CHECK-2p2:       // %bb.0: // %entry
774; CHECK-2p2-NEXT:    ptrue p0.d
775; CHECK-2p2-NEXT:    uxtb z0.d, p0/z, z1.d
776; CHECK-2p2-NEXT:    ret
777entry:
778  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
779  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
780  ret <vscale x 2 x i64> %0
781}
782
783define <vscale x 2 x i64> @test_svuxtb_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
784; CHECK-LABEL: test_svuxtb_nxv2i64_ptrue:
785; CHECK:       // %bb.0: // %entry
786; CHECK-NEXT:    ptrue p0.d
787; CHECK-NEXT:    movprfx z0, z2
788; CHECK-NEXT:    uxtb z0.d, p0/m, z2.d
789; CHECK-NEXT:    ret
790;
791; CHECK-2p2-LABEL: test_svuxtb_nxv2i64_ptrue:
792; CHECK-2p2:       // %bb.0: // %entry
793; CHECK-2p2-NEXT:    ptrue p0.d
794; CHECK-2p2-NEXT:    uxtb z0.d, p0/z, z2.d
795; CHECK-2p2-NEXT:    ret
796entry:
797  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
798  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y)
799  ret <vscale x 2 x i64> %0
800}
801
802define <vscale x 4 x i32> @test_svsxth_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) {
803; CHECK-LABEL: test_svsxth_nxv4i32_ptrue_u:
804; CHECK:       // %bb.0: // %entry
805; CHECK-NEXT:    ptrue p0.s
806; CHECK-NEXT:    movprfx z0, z1
807; CHECK-NEXT:    sxth z0.s, p0/m, z1.s
808; CHECK-NEXT:    ret
809;
810; CHECK-2p2-LABEL: test_svsxth_nxv4i32_ptrue_u:
811; CHECK-2p2:       // %bb.0: // %entry
812; CHECK-2p2-NEXT:    ptrue p0.s
813; CHECK-2p2-NEXT:    sxth z0.s, p0/z, z1.s
814; CHECK-2p2-NEXT:    ret
815entry:
816  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
817  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
818  ret <vscale x 4 x i32> %0
819}
820
821define <vscale x 4 x i32> @test_svsxth_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
822; CHECK-LABEL: test_svsxth_nxv4i32_ptrue:
823; CHECK:       // %bb.0: // %entry
824; CHECK-NEXT:    ptrue p0.s
825; CHECK-NEXT:    movprfx z0, z2
826; CHECK-NEXT:    sxth z0.s, p0/m, z2.s
827; CHECK-NEXT:    ret
828;
829; CHECK-2p2-LABEL: test_svsxth_nxv4i32_ptrue:
830; CHECK-2p2:       // %bb.0: // %entry
831; CHECK-2p2-NEXT:    ptrue p0.s
832; CHECK-2p2-NEXT:    sxth z0.s, p0/z, z2.s
833; CHECK-2p2-NEXT:    ret
834entry:
835  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
836  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y)
837  ret <vscale x 4 x i32> %0
838}
839
840define <vscale x 2 x i64> @test_svsxth_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) {
841; CHECK-LABEL: test_svsxth_nxv2i64_ptrue_u:
842; CHECK:       // %bb.0: // %entry
843; CHECK-NEXT:    ptrue p0.d
844; CHECK-NEXT:    movprfx z0, z1
845; CHECK-NEXT:    sxth z0.d, p0/m, z1.d
846; CHECK-NEXT:    ret
847;
848; CHECK-2p2-LABEL: test_svsxth_nxv2i64_ptrue_u:
849; CHECK-2p2:       // %bb.0: // %entry
850; CHECK-2p2-NEXT:    ptrue p0.d
851; CHECK-2p2-NEXT:    sxth z0.d, p0/z, z1.d
852; CHECK-2p2-NEXT:    ret
853entry:
854  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
855  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
856  ret <vscale x 2 x i64> %0
857}
858
859define <vscale x 2 x i64> @test_svsxth_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
860; CHECK-LABEL: test_svsxth_nxv2i64_ptrue:
861; CHECK:       // %bb.0: // %entry
862; CHECK-NEXT:    ptrue p0.d
863; CHECK-NEXT:    movprfx z0, z2
864; CHECK-NEXT:    sxth z0.d, p0/m, z2.d
865; CHECK-NEXT:    ret
866;
867; CHECK-2p2-LABEL: test_svsxth_nxv2i64_ptrue:
868; CHECK-2p2:       // %bb.0: // %entry
869; CHECK-2p2-NEXT:    ptrue p0.d
870; CHECK-2p2-NEXT:    sxth z0.d, p0/z, z2.d
871; CHECK-2p2-NEXT:    ret
872entry:
873  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
874  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y)
875  ret <vscale x 2 x i64> %0
876}
877
878define <vscale x 4 x i32> @test_svuxth_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) {
879; CHECK-LABEL: test_svuxth_nxv4i32_ptrue_u:
880; CHECK:       // %bb.0: // %entry
881; CHECK-NEXT:    ptrue p0.s
882; CHECK-NEXT:    movprfx z0, z1
883; CHECK-NEXT:    uxth z0.s, p0/m, z1.s
884; CHECK-NEXT:    ret
885;
886; CHECK-2p2-LABEL: test_svuxth_nxv4i32_ptrue_u:
887; CHECK-2p2:       // %bb.0: // %entry
888; CHECK-2p2-NEXT:    ptrue p0.s
889; CHECK-2p2-NEXT:    uxth z0.s, p0/z, z1.s
890; CHECK-2p2-NEXT:    ret
891entry:
892  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
893  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
894  ret <vscale x 4 x i32> %0
895}
896
897define <vscale x 4 x i32> @test_svuxth_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
898; CHECK-LABEL: test_svuxth_nxv4i32_ptrue:
899; CHECK:       // %bb.0: // %entry
900; CHECK-NEXT:    ptrue p0.s
901; CHECK-NEXT:    movprfx z0, z2
902; CHECK-NEXT:    uxth z0.s, p0/m, z2.s
903; CHECK-NEXT:    ret
904;
905; CHECK-2p2-LABEL: test_svuxth_nxv4i32_ptrue:
906; CHECK-2p2:       // %bb.0: // %entry
907; CHECK-2p2-NEXT:    ptrue p0.s
908; CHECK-2p2-NEXT:    uxth z0.s, p0/z, z2.s
909; CHECK-2p2-NEXT:    ret
910entry:
911  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
912  %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y)
913  ret <vscale x 4 x i32> %0
914}
915
916define <vscale x 2 x i64> @test_svuxth_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) {
917; CHECK-LABEL: test_svuxth_nxv2i64_ptrue_u:
918; CHECK:       // %bb.0: // %entry
919; CHECK-NEXT:    ptrue p0.d
920; CHECK-NEXT:    movprfx z0, z1
921; CHECK-NEXT:    uxth z0.d, p0/m, z1.d
922; CHECK-NEXT:    ret
923;
924; CHECK-2p2-LABEL: test_svuxth_nxv2i64_ptrue_u:
925; CHECK-2p2:       // %bb.0: // %entry
926; CHECK-2p2-NEXT:    ptrue p0.d
927; CHECK-2p2-NEXT:    uxth z0.d, p0/z, z1.d
928; CHECK-2p2-NEXT:    ret
929entry:
930  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
931  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
932  ret <vscale x 2 x i64> %0
933}
934
935define <vscale x 2 x i64> @test_svuxth_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
936; CHECK-LABEL: test_svuxth_nxv2i64_ptrue:
937; CHECK:       // %bb.0: // %entry
938; CHECK-NEXT:    ptrue p0.d
939; CHECK-NEXT:    movprfx z0, z2
940; CHECK-NEXT:    uxth z0.d, p0/m, z2.d
941; CHECK-NEXT:    ret
942;
943; CHECK-2p2-LABEL: test_svuxth_nxv2i64_ptrue:
944; CHECK-2p2:       // %bb.0: // %entry
945; CHECK-2p2-NEXT:    ptrue p0.d
946; CHECK-2p2-NEXT:    uxth z0.d, p0/z, z2.d
947; CHECK-2p2-NEXT:    ret
948entry:
949  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
950  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y)
951  ret <vscale x 2 x i64> %0
952}
953
954define <vscale x 2 x i64> @test_svsxtw_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) {
955; CHECK-LABEL: test_svsxtw_nxv2i64_ptrue_u:
956; CHECK:       // %bb.0: // %entry
957; CHECK-NEXT:    ptrue p0.d
958; CHECK-NEXT:    movprfx z0, z1
959; CHECK-NEXT:    sxtw z0.d, p0/m, z1.d
960; CHECK-NEXT:    ret
961;
962; CHECK-2p2-LABEL: test_svsxtw_nxv2i64_ptrue_u:
963; CHECK-2p2:       // %bb.0: // %entry
964; CHECK-2p2-NEXT:    ptrue p0.d
965; CHECK-2p2-NEXT:    sxtw z0.d, p0/z, z1.d
966; CHECK-2p2-NEXT:    ret
967entry:
968  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
969  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
970  ret <vscale x 2 x i64> %0
971}
972
973define <vscale x 2 x i64> @test_svsxtw_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
974; CHECK-LABEL: test_svsxtw_nxv2i64_ptrue:
975; CHECK:       // %bb.0: // %entry
976; CHECK-NEXT:    ptrue p0.d
977; CHECK-NEXT:    movprfx z0, z2
978; CHECK-NEXT:    sxtw z0.d, p0/m, z2.d
979; CHECK-NEXT:    ret
980;
981; CHECK-2p2-LABEL: test_svsxtw_nxv2i64_ptrue:
982; CHECK-2p2:       // %bb.0: // %entry
983; CHECK-2p2-NEXT:    ptrue p0.d
984; CHECK-2p2-NEXT:    sxtw z0.d, p0/z, z2.d
985; CHECK-2p2-NEXT:    ret
986entry:
987  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
988  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y)
989  ret <vscale x 2 x i64> %0
990}
991
992define <vscale x 2 x i64> @test_svuxtw_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) {
993; CHECK-LABEL: test_svuxtw_nxv2i64_ptrue_u:
994; CHECK:       // %bb.0: // %entry
995; CHECK-NEXT:    ptrue p0.d
996; CHECK-NEXT:    movprfx z0, z1
997; CHECK-NEXT:    uxtw z0.d, p0/m, z1.d
998; CHECK-NEXT:    ret
999;
1000; CHECK-2p2-LABEL: test_svuxtw_nxv2i64_ptrue_u:
1001; CHECK-2p2:       // %bb.0: // %entry
1002; CHECK-2p2-NEXT:    ptrue p0.d
1003; CHECK-2p2-NEXT:    uxtw z0.d, p0/z, z1.d
1004; CHECK-2p2-NEXT:    ret
1005entry:
1006  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
1007  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
1008  ret <vscale x 2 x i64> %0
1009}
1010
1011define <vscale x 2 x i64> @test_svuxtw_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
1012; CHECK-LABEL: test_svuxtw_nxv2i64_ptrue:
1013; CHECK:       // %bb.0: // %entry
1014; CHECK-NEXT:    ptrue p0.d
1015; CHECK-NEXT:    movprfx z0, z2
1016; CHECK-NEXT:    uxtw z0.d, p0/m, z2.d
1017; CHECK-NEXT:    ret
1018;
1019; CHECK-2p2-LABEL: test_svuxtw_nxv2i64_ptrue:
1020; CHECK-2p2:       // %bb.0: // %entry
1021; CHECK-2p2-NEXT:    ptrue p0.d
1022; CHECK-2p2-NEXT:    uxtw z0.d, p0/z, z2.d
1023; CHECK-2p2-NEXT:    ret
1024entry:
1025  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
1026  %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y)
1027  ret <vscale x 2 x i64> %0
1028}
1029