1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mattr=+bf16,+sve < %s | FileCheck %s 3; RUN: llc -mattr=+bf16,+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2 4 5; RUN: llc -mattr=+bf16,+sme -force-streaming < %s | FileCheck %s 6; RUN: llc -mattr=+bf16,+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2 7 8target triple = "aarch64-linux" 9 10define <vscale x 16 x i8> @test_svcls_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) { 11; CHECK-LABEL: test_svcls_s8_x_1: 12; CHECK: // %bb.0: // %entry 13; CHECK-NEXT: cls z0.b, p0/m, z0.b 14; CHECK-NEXT: ret 15; 16; CHECK-2p2-LABEL: test_svcls_s8_x_1: 17; CHECK-2p2: // %bb.0: // %entry 18; CHECK-2p2-NEXT: cls z0.b, p0/z, z0.b 19; CHECK-2p2-NEXT: ret 20entry: 21 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 22 ret <vscale x 16 x i8> %0 23} 24 25define <vscale x 16 x i8> @test_svcls_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 26; CHECK-LABEL: test_svcls_s8_x_2: 27; CHECK: // %bb.0: // %entry 28; CHECK-NEXT: movprfx z0, z1 29; CHECK-NEXT: cls z0.b, p0/m, z1.b 30; CHECK-NEXT: ret 31; 32; CHECK-2p2-LABEL: test_svcls_s8_x_2: 33; CHECK-2p2: // %bb.0: // %entry 34; CHECK-2p2-NEXT: cls z0.b, p0/z, z1.b 35; CHECK-2p2-NEXT: ret 36entry: 37 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 38 ret <vscale x 16 x i8> %0 39} 40 41define <vscale x 16 x i8> @test_svcls_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 42; CHECK-LABEL: test_svcls_s8_z: 43; CHECK: // %bb.0: // %entry 44; CHECK-NEXT: mov z0.b, #0 // =0x0 45; CHECK-NEXT: cls z0.b, p0/m, z1.b 46; CHECK-NEXT: ret 47; 48; CHECK-2p2-LABEL: test_svcls_s8_z: 49; CHECK-2p2: // %bb.0: // %entry 50; CHECK-2p2-NEXT: cls z0.b, p0/z, z1.b 51; CHECK-2p2-NEXT: ret 52entry: 53 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 54 ret <vscale x 16 x i8> %0 55} 56 57define <vscale x 8 x i16> @test_svcls_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) { 58; CHECK-LABEL: test_svcls_s16_x_1: 59; CHECK: // %bb.0: // %entry 60; CHECK-NEXT: cls z0.h, p0/m, z0.h 61; CHECK-NEXT: ret 62; 63; CHECK-2p2-LABEL: test_svcls_s16_x_1: 64; CHECK-2p2: // %bb.0: // %entry 65; CHECK-2p2-NEXT: cls z0.h, p0/z, z0.h 66; CHECK-2p2-NEXT: ret 67entry: 68 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 69 ret <vscale x 8 x i16> %0 70} 71 72define <vscale x 8 x i16> @test_svcls_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 73; CHECK-LABEL: test_svcls_s16_x_2: 74; CHECK: // %bb.0: // %entry 75; CHECK-NEXT: movprfx z0, z1 76; CHECK-NEXT: cls z0.h, p0/m, z1.h 77; CHECK-NEXT: ret 78; 79; CHECK-2p2-LABEL: test_svcls_s16_x_2: 80; CHECK-2p2: // %bb.0: // %entry 81; CHECK-2p2-NEXT: cls z0.h, p0/z, z1.h 82; CHECK-2p2-NEXT: ret 83entry: 84 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 85 ret <vscale x 8 x i16> %0 86} 87 88define <vscale x 8 x i16> @test_svcls_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 89; CHECK-LABEL: test_svcls_s16_z: 90; CHECK: // %bb.0: // %entry 91; CHECK-NEXT: mov z0.h, #0 // =0x0 92; CHECK-NEXT: cls z0.h, p0/m, z1.h 93; CHECK-NEXT: ret 94; 95; CHECK-2p2-LABEL: test_svcls_s16_z: 96; CHECK-2p2: // %bb.0: // %entry 97; CHECK-2p2-NEXT: cls z0.h, p0/z, z1.h 98; CHECK-2p2-NEXT: ret 99entry: 100 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 101 ret <vscale x 8 x i16> %0 102} 103 104define <vscale x 4 x i32> @test_svcls_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) { 105; CHECK-LABEL: test_svcls_s32_x_1: 106; CHECK: // %bb.0: // %entry 107; CHECK-NEXT: cls z0.s, p0/m, z0.s 108; CHECK-NEXT: ret 109; 110; CHECK-2p2-LABEL: test_svcls_s32_x_1: 111; CHECK-2p2: // %bb.0: // %entry 112; CHECK-2p2-NEXT: cls z0.s, p0/z, z0.s 113; CHECK-2p2-NEXT: ret 114entry: 115 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 116 ret <vscale x 4 x i32> %0 117} 118 119define <vscale x 4 x i32> @test_svcls_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 120; CHECK-LABEL: test_svcls_s32_x_2: 121; CHECK: // %bb.0: // %entry 122; CHECK-NEXT: movprfx z0, z1 123; CHECK-NEXT: cls z0.s, p0/m, z1.s 124; CHECK-NEXT: ret 125; 126; CHECK-2p2-LABEL: test_svcls_s32_x_2: 127; CHECK-2p2: // %bb.0: // %entry 128; CHECK-2p2-NEXT: cls z0.s, p0/z, z1.s 129; CHECK-2p2-NEXT: ret 130entry: 131 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 132 ret <vscale x 4 x i32> %0 133} 134 135define <vscale x 4 x i32> @test_svcls_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 136; CHECK-LABEL: test_svcls_s32_z: 137; CHECK: // %bb.0: // %entry 138; CHECK-NEXT: mov z0.s, #0 // =0x0 139; CHECK-NEXT: cls z0.s, p0/m, z1.s 140; CHECK-NEXT: ret 141; 142; CHECK-2p2-LABEL: test_svcls_s32_z: 143; CHECK-2p2: // %bb.0: // %entry 144; CHECK-2p2-NEXT: cls z0.s, p0/z, z1.s 145; CHECK-2p2-NEXT: ret 146entry: 147 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 148 ret <vscale x 4 x i32> %0 149} 150 151define <vscale x 2 x i64> @test_svcls_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) { 152; CHECK-LABEL: test_svcls_s64_x_1: 153; CHECK: // %bb.0: // %entry 154; CHECK-NEXT: cls z0.d, p0/m, z0.d 155; CHECK-NEXT: ret 156; 157; CHECK-2p2-LABEL: test_svcls_s64_x_1: 158; CHECK-2p2: // %bb.0: // %entry 159; CHECK-2p2-NEXT: cls z0.d, p0/z, z0.d 160; CHECK-2p2-NEXT: ret 161entry: 162 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 163 ret <vscale x 2 x i64> %0 164} 165 166define <vscale x 2 x i64> @test_svcls_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 167; CHECK-LABEL: test_svcls_s64_x_2: 168; CHECK: // %bb.0: // %entry 169; CHECK-NEXT: movprfx z0, z1 170; CHECK-NEXT: cls z0.d, p0/m, z1.d 171; CHECK-NEXT: ret 172; 173; CHECK-2p2-LABEL: test_svcls_s64_x_2: 174; CHECK-2p2: // %bb.0: // %entry 175; CHECK-2p2-NEXT: cls z0.d, p0/z, z1.d 176; CHECK-2p2-NEXT: ret 177entry: 178 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 179 ret <vscale x 2 x i64> %0 180} 181 182define <vscale x 2 x i64> @test_svcls_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 183; CHECK-LABEL: test_svcls_s64_z: 184; CHECK: // %bb.0: // %entry 185; CHECK-NEXT: mov z0.d, #0 // =0x0 186; CHECK-NEXT: cls z0.d, p0/m, z1.d 187; CHECK-NEXT: ret 188; 189; CHECK-2p2-LABEL: test_svcls_s64_z: 190; CHECK-2p2: // %bb.0: // %entry 191; CHECK-2p2-NEXT: cls z0.d, p0/z, z1.d 192; CHECK-2p2-NEXT: ret 193entry: 194 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 195 ret <vscale x 2 x i64> %0 196} 197 198define <vscale x 16 x i8> @test_svclz_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) { 199; CHECK-LABEL: test_svclz_s8_x_1: 200; CHECK: // %bb.0: // %entry 201; CHECK-NEXT: clz z0.b, p0/m, z0.b 202; CHECK-NEXT: ret 203; 204; CHECK-2p2-LABEL: test_svclz_s8_x_1: 205; CHECK-2p2: // %bb.0: // %entry 206; CHECK-2p2-NEXT: clz z0.b, p0/z, z0.b 207; CHECK-2p2-NEXT: ret 208entry: 209 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 210 ret <vscale x 16 x i8> %0 211} 212 213define <vscale x 16 x i8> @test_svclz_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 214; CHECK-LABEL: test_svclz_s8_x_2: 215; CHECK: // %bb.0: // %entry 216; CHECK-NEXT: movprfx z0, z1 217; CHECK-NEXT: clz z0.b, p0/m, z1.b 218; CHECK-NEXT: ret 219; 220; CHECK-2p2-LABEL: test_svclz_s8_x_2: 221; CHECK-2p2: // %bb.0: // %entry 222; CHECK-2p2-NEXT: clz z0.b, p0/z, z1.b 223; CHECK-2p2-NEXT: ret 224entry: 225 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 226 ret <vscale x 16 x i8> %0 227} 228 229define <vscale x 16 x i8> @test_svclz_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 230; CHECK-LABEL: test_svclz_s8_z: 231; CHECK: // %bb.0: // %entry 232; CHECK-NEXT: mov z0.b, #0 // =0x0 233; CHECK-NEXT: clz z0.b, p0/m, z1.b 234; CHECK-NEXT: ret 235; 236; CHECK-2p2-LABEL: test_svclz_s8_z: 237; CHECK-2p2: // %bb.0: // %entry 238; CHECK-2p2-NEXT: clz z0.b, p0/z, z1.b 239; CHECK-2p2-NEXT: ret 240entry: 241 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 242 ret <vscale x 16 x i8> %0 243} 244 245define <vscale x 8 x i16> @test_svclz_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) { 246; CHECK-LABEL: test_svclz_s16_x_1: 247; CHECK: // %bb.0: // %entry 248; CHECK-NEXT: clz z0.h, p0/m, z0.h 249; CHECK-NEXT: ret 250; 251; CHECK-2p2-LABEL: test_svclz_s16_x_1: 252; CHECK-2p2: // %bb.0: // %entry 253; CHECK-2p2-NEXT: clz z0.h, p0/z, z0.h 254; CHECK-2p2-NEXT: ret 255entry: 256 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 257 ret <vscale x 8 x i16> %0 258} 259 260define <vscale x 8 x i16> @test_svclz_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 261; CHECK-LABEL: test_svclz_s16_x_2: 262; CHECK: // %bb.0: // %entry 263; CHECK-NEXT: movprfx z0, z1 264; CHECK-NEXT: clz z0.h, p0/m, z1.h 265; CHECK-NEXT: ret 266; 267; CHECK-2p2-LABEL: test_svclz_s16_x_2: 268; CHECK-2p2: // %bb.0: // %entry 269; CHECK-2p2-NEXT: clz z0.h, p0/z, z1.h 270; CHECK-2p2-NEXT: ret 271entry: 272 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 273 ret <vscale x 8 x i16> %0 274} 275 276define <vscale x 8 x i16> @test_svclz_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 277; CHECK-LABEL: test_svclz_s16_z: 278; CHECK: // %bb.0: // %entry 279; CHECK-NEXT: mov z0.h, #0 // =0x0 280; CHECK-NEXT: clz z0.h, p0/m, z1.h 281; CHECK-NEXT: ret 282; 283; CHECK-2p2-LABEL: test_svclz_s16_z: 284; CHECK-2p2: // %bb.0: // %entry 285; CHECK-2p2-NEXT: clz z0.h, p0/z, z1.h 286; CHECK-2p2-NEXT: ret 287entry: 288 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 289 ret <vscale x 8 x i16> %0 290} 291 292define <vscale x 4 x i32> @test_svclz_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) { 293; CHECK-LABEL: test_svclz_s32_x_1: 294; CHECK: // %bb.0: // %entry 295; CHECK-NEXT: clz z0.s, p0/m, z0.s 296; CHECK-NEXT: ret 297; 298; CHECK-2p2-LABEL: test_svclz_s32_x_1: 299; CHECK-2p2: // %bb.0: // %entry 300; CHECK-2p2-NEXT: clz z0.s, p0/z, z0.s 301; CHECK-2p2-NEXT: ret 302entry: 303 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 304 ret <vscale x 4 x i32> %0 305} 306 307define <vscale x 4 x i32> @test_svclz_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 308; CHECK-LABEL: test_svclz_s32_x_2: 309; CHECK: // %bb.0: // %entry 310; CHECK-NEXT: movprfx z0, z1 311; CHECK-NEXT: clz z0.s, p0/m, z1.s 312; CHECK-NEXT: ret 313; 314; CHECK-2p2-LABEL: test_svclz_s32_x_2: 315; CHECK-2p2: // %bb.0: // %entry 316; CHECK-2p2-NEXT: clz z0.s, p0/z, z1.s 317; CHECK-2p2-NEXT: ret 318entry: 319 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 320 ret <vscale x 4 x i32> %0 321} 322 323define <vscale x 4 x i32> @test_svclz_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 324; CHECK-LABEL: test_svclz_s32_z: 325; CHECK: // %bb.0: // %entry 326; CHECK-NEXT: mov z0.s, #0 // =0x0 327; CHECK-NEXT: clz z0.s, p0/m, z1.s 328; CHECK-NEXT: ret 329; 330; CHECK-2p2-LABEL: test_svclz_s32_z: 331; CHECK-2p2: // %bb.0: // %entry 332; CHECK-2p2-NEXT: clz z0.s, p0/z, z1.s 333; CHECK-2p2-NEXT: ret 334entry: 335 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 336 ret <vscale x 4 x i32> %0 337} 338 339define <vscale x 2 x i64> @test_svclz_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) { 340; CHECK-LABEL: test_svclz_s64_x_1: 341; CHECK: // %bb.0: // %entry 342; CHECK-NEXT: clz z0.d, p0/m, z0.d 343; CHECK-NEXT: ret 344; 345; CHECK-2p2-LABEL: test_svclz_s64_x_1: 346; CHECK-2p2: // %bb.0: // %entry 347; CHECK-2p2-NEXT: clz z0.d, p0/z, z0.d 348; CHECK-2p2-NEXT: ret 349entry: 350 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 351 ret <vscale x 2 x i64> %0 352} 353 354define <vscale x 2 x i64> @test_svclz_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 355; CHECK-LABEL: test_svclz_s64_x_2: 356; CHECK: // %bb.0: // %entry 357; CHECK-NEXT: movprfx z0, z1 358; CHECK-NEXT: clz z0.d, p0/m, z1.d 359; CHECK-NEXT: ret 360; 361; CHECK-2p2-LABEL: test_svclz_s64_x_2: 362; CHECK-2p2: // %bb.0: // %entry 363; CHECK-2p2-NEXT: clz z0.d, p0/z, z1.d 364; CHECK-2p2-NEXT: ret 365entry: 366 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 367 ret <vscale x 2 x i64> %0 368} 369 370define <vscale x 2 x i64> @test_svclz_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 371; CHECK-LABEL: test_svclz_s64_z: 372; CHECK: // %bb.0: // %entry 373; CHECK-NEXT: mov z0.d, #0 // =0x0 374; CHECK-NEXT: clz z0.d, p0/m, z1.d 375; CHECK-NEXT: ret 376; 377; CHECK-2p2-LABEL: test_svclz_s64_z: 378; CHECK-2p2: // %bb.0: // %entry 379; CHECK-2p2-NEXT: clz z0.d, p0/z, z1.d 380; CHECK-2p2-NEXT: ret 381entry: 382 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 383 ret <vscale x 2 x i64> %0 384} 385 386define <vscale x 16 x i8> @test_svcnt_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) { 387; CHECK-LABEL: test_svcnt_s8_x_1: 388; CHECK: // %bb.0: // %entry 389; CHECK-NEXT: cnt z0.b, p0/m, z0.b 390; CHECK-NEXT: ret 391; 392; CHECK-2p2-LABEL: test_svcnt_s8_x_1: 393; CHECK-2p2: // %bb.0: // %entry 394; CHECK-2p2-NEXT: cnt z0.b, p0/z, z0.b 395; CHECK-2p2-NEXT: ret 396entry: 397 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 398 ret <vscale x 16 x i8> %0 399} 400 401define <vscale x 16 x i8> @test_svcnt_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 402; CHECK-LABEL: test_svcnt_s8_x_2: 403; CHECK: // %bb.0: // %entry 404; CHECK-NEXT: movprfx z0, z1 405; CHECK-NEXT: cnt z0.b, p0/m, z1.b 406; CHECK-NEXT: ret 407; 408; CHECK-2p2-LABEL: test_svcnt_s8_x_2: 409; CHECK-2p2: // %bb.0: // %entry 410; CHECK-2p2-NEXT: cnt z0.b, p0/z, z1.b 411; CHECK-2p2-NEXT: ret 412entry: 413 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 414 ret <vscale x 16 x i8> %0 415} 416 417define <vscale x 16 x i8> @test_svcnt_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 418; CHECK-LABEL: test_svcnt_s8_z: 419; CHECK: // %bb.0: // %entry 420; CHECK-NEXT: mov z0.b, #0 // =0x0 421; CHECK-NEXT: cnt z0.b, p0/m, z1.b 422; CHECK-NEXT: ret 423; 424; CHECK-2p2-LABEL: test_svcnt_s8_z: 425; CHECK-2p2: // %bb.0: // %entry 426; CHECK-2p2-NEXT: cnt z0.b, p0/z, z1.b 427; CHECK-2p2-NEXT: ret 428entry: 429 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 430 ret <vscale x 16 x i8> %0 431} 432 433define <vscale x 8 x i16> @test_svcnt_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) { 434; CHECK-LABEL: test_svcnt_s16_x_1: 435; CHECK: // %bb.0: // %entry 436; CHECK-NEXT: cnt z0.h, p0/m, z0.h 437; CHECK-NEXT: ret 438; 439; CHECK-2p2-LABEL: test_svcnt_s16_x_1: 440; CHECK-2p2: // %bb.0: // %entry 441; CHECK-2p2-NEXT: cnt z0.h, p0/z, z0.h 442; CHECK-2p2-NEXT: ret 443entry: 444 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 445 ret <vscale x 8 x i16> %0 446} 447 448define <vscale x 8 x i16> @test_svcnt_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 449; CHECK-LABEL: test_svcnt_s16_x_2: 450; CHECK: // %bb.0: // %entry 451; CHECK-NEXT: movprfx z0, z1 452; CHECK-NEXT: cnt z0.h, p0/m, z1.h 453; CHECK-NEXT: ret 454; 455; CHECK-2p2-LABEL: test_svcnt_s16_x_2: 456; CHECK-2p2: // %bb.0: // %entry 457; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 458; CHECK-2p2-NEXT: ret 459entry: 460 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 461 ret <vscale x 8 x i16> %0 462} 463 464define <vscale x 8 x i16> @test_svcnt_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 465; CHECK-LABEL: test_svcnt_s16_z: 466; CHECK: // %bb.0: // %entry 467; CHECK-NEXT: mov z0.h, #0 // =0x0 468; CHECK-NEXT: cnt z0.h, p0/m, z1.h 469; CHECK-NEXT: ret 470; 471; CHECK-2p2-LABEL: test_svcnt_s16_z: 472; CHECK-2p2: // %bb.0: // %entry 473; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 474; CHECK-2p2-NEXT: ret 475entry: 476 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 477 ret <vscale x 8 x i16> %0 478} 479 480define <vscale x 4 x i32> @test_svcnt_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) { 481; CHECK-LABEL: test_svcnt_s32_x_1: 482; CHECK: // %bb.0: // %entry 483; CHECK-NEXT: cnt z0.s, p0/m, z0.s 484; CHECK-NEXT: ret 485; 486; CHECK-2p2-LABEL: test_svcnt_s32_x_1: 487; CHECK-2p2: // %bb.0: // %entry 488; CHECK-2p2-NEXT: cnt z0.s, p0/z, z0.s 489; CHECK-2p2-NEXT: ret 490entry: 491 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 492 ret <vscale x 4 x i32> %0 493} 494 495define <vscale x 4 x i32> @test_svcnt_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 496; CHECK-LABEL: test_svcnt_s32_x_2: 497; CHECK: // %bb.0: // %entry 498; CHECK-NEXT: movprfx z0, z1 499; CHECK-NEXT: cnt z0.s, p0/m, z1.s 500; CHECK-NEXT: ret 501; 502; CHECK-2p2-LABEL: test_svcnt_s32_x_2: 503; CHECK-2p2: // %bb.0: // %entry 504; CHECK-2p2-NEXT: cnt z0.s, p0/z, z1.s 505; CHECK-2p2-NEXT: ret 506entry: 507 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 508 ret <vscale x 4 x i32> %0 509} 510 511define <vscale x 4 x i32> @test_svcnt_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 512; CHECK-LABEL: test_svcnt_s32_z: 513; CHECK: // %bb.0: // %entry 514; CHECK-NEXT: mov z0.s, #0 // =0x0 515; CHECK-NEXT: cnt z0.s, p0/m, z1.s 516; CHECK-NEXT: ret 517; 518; CHECK-2p2-LABEL: test_svcnt_s32_z: 519; CHECK-2p2: // %bb.0: // %entry 520; CHECK-2p2-NEXT: cnt z0.s, p0/z, z1.s 521; CHECK-2p2-NEXT: ret 522entry: 523 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 524 ret <vscale x 4 x i32> %0 525} 526 527define <vscale x 2 x i64> @test_svcnt_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) { 528; CHECK-LABEL: test_svcnt_s64_x_1: 529; CHECK: // %bb.0: // %entry 530; CHECK-NEXT: cnt z0.d, p0/m, z0.d 531; CHECK-NEXT: ret 532; 533; CHECK-2p2-LABEL: test_svcnt_s64_x_1: 534; CHECK-2p2: // %bb.0: // %entry 535; CHECK-2p2-NEXT: cnt z0.d, p0/z, z0.d 536; CHECK-2p2-NEXT: ret 537entry: 538 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 539 ret <vscale x 2 x i64> %0 540} 541 542define <vscale x 2 x i64> @test_svcnt_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 543; CHECK-LABEL: test_svcnt_s64_x_2: 544; CHECK: // %bb.0: // %entry 545; CHECK-NEXT: movprfx z0, z1 546; CHECK-NEXT: cnt z0.d, p0/m, z1.d 547; CHECK-NEXT: ret 548; 549; CHECK-2p2-LABEL: test_svcnt_s64_x_2: 550; CHECK-2p2: // %bb.0: // %entry 551; CHECK-2p2-NEXT: cnt z0.d, p0/z, z1.d 552; CHECK-2p2-NEXT: ret 553entry: 554 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 555 ret <vscale x 2 x i64> %0 556} 557 558define <vscale x 2 x i64> @test_svcnt_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 559; CHECK-LABEL: test_svcnt_s64_z: 560; CHECK: // %bb.0: // %entry 561; CHECK-NEXT: mov z0.d, #0 // =0x0 562; CHECK-NEXT: cnt z0.d, p0/m, z1.d 563; CHECK-NEXT: ret 564; 565; CHECK-2p2-LABEL: test_svcnt_s64_z: 566; CHECK-2p2: // %bb.0: // %entry 567; CHECK-2p2-NEXT: cnt z0.d, p0/z, z1.d 568; CHECK-2p2-NEXT: ret 569entry: 570 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 571 ret <vscale x 2 x i64> %0 572} 573 574define <vscale x 8 x i16> @test_svcnt_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) { 575; CHECK-LABEL: test_svcnt_f16_x_1: 576; CHECK: // %bb.0: // %entry 577; CHECK-NEXT: cnt z0.h, p0/m, z0.h 578; CHECK-NEXT: ret 579; 580; CHECK-2p2-LABEL: test_svcnt_f16_x_1: 581; CHECK-2p2: // %bb.0: // %entry 582; CHECK-2p2-NEXT: cnt z0.h, p0/z, z0.h 583; CHECK-2p2-NEXT: ret 584entry: 585 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x) 586 ret <vscale x 8 x i16> %0 587} 588 589define <vscale x 8 x i16> @test_svcnt_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) { 590; CHECK-LABEL: test_svcnt_f16_x_2: 591; CHECK: // %bb.0: // %entry 592; CHECK-NEXT: movprfx z0, z1 593; CHECK-NEXT: cnt z0.h, p0/m, z1.h 594; CHECK-NEXT: ret 595; 596; CHECK-2p2-LABEL: test_svcnt_f16_x_2: 597; CHECK-2p2: // %bb.0: // %entry 598; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 599; CHECK-2p2-NEXT: ret 600entry: 601 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x) 602 ret <vscale x 8 x i16> %0 603} 604 605define <vscale x 8 x i16> @test_svcnt_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) { 606; CHECK-LABEL: test_svcnt_f16_z: 607; CHECK: // %bb.0: // %entry 608; CHECK-NEXT: mov z0.h, #0 // =0x0 609; CHECK-NEXT: cnt z0.h, p0/m, z1.h 610; CHECK-NEXT: ret 611; 612; CHECK-2p2-LABEL: test_svcnt_f16_z: 613; CHECK-2p2: // %bb.0: // %entry 614; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 615; CHECK-2p2-NEXT: ret 616entry: 617 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x) 618 ret <vscale x 8 x i16> %0 619} 620 621define <vscale x 8 x i16> @test_svcnt_bf16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %x) { 622; CHECK-LABEL: test_svcnt_bf16_x_1: 623; CHECK: // %bb.0: // %entry 624; CHECK-NEXT: cnt z0.h, p0/m, z0.h 625; CHECK-NEXT: ret 626; 627; CHECK-2p2-LABEL: test_svcnt_bf16_x_1: 628; CHECK-2p2: // %bb.0: // %entry 629; CHECK-2p2-NEXT: cnt z0.h, p0/z, z0.h 630; CHECK-2p2-NEXT: ret 631entry: 632 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %x) 633 ret <vscale x 8 x i16> %0 634} 635 636define <vscale x 8 x i16> @test_svcnt_bf16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x bfloat> %x) { 637; CHECK-LABEL: test_svcnt_bf16_x_2: 638; CHECK: // %bb.0: // %entry 639; CHECK-NEXT: movprfx z0, z1 640; CHECK-NEXT: cnt z0.h, p0/m, z1.h 641; CHECK-NEXT: ret 642; 643; CHECK-2p2-LABEL: test_svcnt_bf16_x_2: 644; CHECK-2p2: // %bb.0: // %entry 645; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 646; CHECK-2p2-NEXT: ret 647entry: 648 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %x) 649 ret <vscale x 8 x i16> %0 650} 651 652define <vscale x 8 x i16> @test_svcnt_bf16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x bfloat> %x) { 653; CHECK-LABEL: test_svcnt_bf16_z: 654; CHECK: // %bb.0: // %entry 655; CHECK-NEXT: mov z0.h, #0 // =0x0 656; CHECK-NEXT: cnt z0.h, p0/m, z1.h 657; CHECK-NEXT: ret 658; 659; CHECK-2p2-LABEL: test_svcnt_bf16_z: 660; CHECK-2p2: // %bb.0: // %entry 661; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 662; CHECK-2p2-NEXT: ret 663entry: 664 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %x) 665 ret <vscale x 8 x i16> %0 666} 667 668define <vscale x 4 x i32> @test_svcnt_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) { 669; CHECK-LABEL: test_svcnt_f32_x_1: 670; CHECK: // %bb.0: // %entry 671; CHECK-NEXT: cnt z0.s, p0/m, z0.s 672; CHECK-NEXT: ret 673; 674; CHECK-2p2-LABEL: test_svcnt_f32_x_1: 675; CHECK-2p2: // %bb.0: // %entry 676; CHECK-2p2-NEXT: cnt z0.s, p0/z, z0.s 677; CHECK-2p2-NEXT: ret 678entry: 679 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x) 680 ret <vscale x 4 x i32> %0 681} 682 683define <vscale x 4 x i32> @test_svcnt_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) { 684; CHECK-LABEL: test_svcnt_f32_x_2: 685; CHECK: // %bb.0: // %entry 686; CHECK-NEXT: movprfx z0, z1 687; CHECK-NEXT: cnt z0.s, p0/m, z1.s 688; CHECK-NEXT: ret 689; 690; CHECK-2p2-LABEL: test_svcnt_f32_x_2: 691; CHECK-2p2: // %bb.0: // %entry 692; CHECK-2p2-NEXT: cnt z0.s, p0/z, z1.s 693; CHECK-2p2-NEXT: ret 694entry: 695 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x) 696 ret <vscale x 4 x i32> %0 697} 698 699define <vscale x 4 x i32> @test_svcnt_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) { 700; CHECK-LABEL: test_svcnt_f32_z: 701; CHECK: // %bb.0: // %entry 702; CHECK-NEXT: mov z0.s, #0 // =0x0 703; CHECK-NEXT: cnt z0.s, p0/m, z1.s 704; CHECK-NEXT: ret 705; 706; CHECK-2p2-LABEL: test_svcnt_f32_z: 707; CHECK-2p2: // %bb.0: // %entry 708; CHECK-2p2-NEXT: cnt z0.s, p0/z, z1.s 709; CHECK-2p2-NEXT: ret 710entry: 711 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x) 712 ret <vscale x 4 x i32> %0 713} 714 715define <vscale x 2 x i64> @test_svcnt_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) { 716; CHECK-LABEL: test_svcnt_f64_x_1: 717; CHECK: // %bb.0: // %entry 718; CHECK-NEXT: cnt z0.d, p0/m, z0.d 719; CHECK-NEXT: ret 720; 721; CHECK-2p2-LABEL: test_svcnt_f64_x_1: 722; CHECK-2p2: // %bb.0: // %entry 723; CHECK-2p2-NEXT: cnt z0.d, p0/z, z0.d 724; CHECK-2p2-NEXT: ret 725entry: 726 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x) 727 ret <vscale x 2 x i64> %0 728} 729 730define <vscale x 2 x i64> @test_svcnt_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) { 731; CHECK-LABEL: test_svcnt_f64_x_2: 732; CHECK: // %bb.0: // %entry 733; CHECK-NEXT: movprfx z0, z1 734; CHECK-NEXT: cnt z0.d, p0/m, z1.d 735; CHECK-NEXT: ret 736; 737; CHECK-2p2-LABEL: test_svcnt_f64_x_2: 738; CHECK-2p2: // %bb.0: // %entry 739; CHECK-2p2-NEXT: cnt z0.d, p0/z, z1.d 740; CHECK-2p2-NEXT: ret 741entry: 742 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x) 743 ret <vscale x 2 x i64> %0 744} 745 746define <vscale x 2 x i64> @test_svcnt_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) { 747; CHECK-LABEL: test_svcnt_f64_z: 748; CHECK: // %bb.0: // %entry 749; CHECK-NEXT: mov z0.d, #0 // =0x0 750; CHECK-NEXT: cnt z0.d, p0/m, z1.d 751; CHECK-NEXT: ret 752; 753; CHECK-2p2-LABEL: test_svcnt_f64_z: 754; CHECK-2p2: // %bb.0: // %entry 755; CHECK-2p2-NEXT: cnt z0.d, p0/z, z1.d 756; CHECK-2p2-NEXT: ret 757entry: 758 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x) 759 ret <vscale x 2 x i64> %0 760} 761 762define <vscale x 16 x i8> @test_svcnot_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) { 763; CHECK-LABEL: test_svcnot_s8_x_1: 764; CHECK: // %bb.0: // %entry 765; CHECK-NEXT: cnot z0.b, p0/m, z0.b 766; CHECK-NEXT: ret 767; 768; CHECK-2p2-LABEL: test_svcnot_s8_x_1: 769; CHECK-2p2: // %bb.0: // %entry 770; CHECK-2p2-NEXT: cnot z0.b, p0/z, z0.b 771; CHECK-2p2-NEXT: ret 772entry: 773 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 774 ret <vscale x 16 x i8> %0 775} 776 777define <vscale x 16 x i8> @test_svcnot_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 778; CHECK-LABEL: test_svcnot_s8_x_2: 779; CHECK: // %bb.0: // %entry 780; CHECK-NEXT: movprfx z0, z1 781; CHECK-NEXT: cnot z0.b, p0/m, z1.b 782; CHECK-NEXT: ret 783; 784; CHECK-2p2-LABEL: test_svcnot_s8_x_2: 785; CHECK-2p2: // %bb.0: // %entry 786; CHECK-2p2-NEXT: cnot z0.b, p0/z, z1.b 787; CHECK-2p2-NEXT: ret 788entry: 789 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 790 ret <vscale x 16 x i8> %0 791} 792 793define <vscale x 16 x i8> @test_svcnot_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 794; CHECK-LABEL: test_svcnot_s8_z: 795; CHECK: // %bb.0: // %entry 796; CHECK-NEXT: mov z0.b, #0 // =0x0 797; CHECK-NEXT: cnot z0.b, p0/m, z1.b 798; CHECK-NEXT: ret 799; 800; CHECK-2p2-LABEL: test_svcnot_s8_z: 801; CHECK-2p2: // %bb.0: // %entry 802; CHECK-2p2-NEXT: cnot z0.b, p0/z, z1.b 803; CHECK-2p2-NEXT: ret 804entry: 805 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 806 ret <vscale x 16 x i8> %0 807} 808 809define <vscale x 8 x i16> @test_svcnot_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) { 810; CHECK-LABEL: test_svcnot_s16_x_1: 811; CHECK: // %bb.0: // %entry 812; CHECK-NEXT: cnot z0.h, p0/m, z0.h 813; CHECK-NEXT: ret 814; 815; CHECK-2p2-LABEL: test_svcnot_s16_x_1: 816; CHECK-2p2: // %bb.0: // %entry 817; CHECK-2p2-NEXT: cnot z0.h, p0/z, z0.h 818; CHECK-2p2-NEXT: ret 819entry: 820 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 821 ret <vscale x 8 x i16> %0 822} 823 824define <vscale x 8 x i16> @test_svcnot_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 825; CHECK-LABEL: test_svcnot_s16_x_2: 826; CHECK: // %bb.0: // %entry 827; CHECK-NEXT: movprfx z0, z1 828; CHECK-NEXT: cnot z0.h, p0/m, z1.h 829; CHECK-NEXT: ret 830; 831; CHECK-2p2-LABEL: test_svcnot_s16_x_2: 832; CHECK-2p2: // %bb.0: // %entry 833; CHECK-2p2-NEXT: cnot z0.h, p0/z, z1.h 834; CHECK-2p2-NEXT: ret 835entry: 836 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 837 ret <vscale x 8 x i16> %0 838} 839 840define <vscale x 8 x i16> @test_svcnot_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 841; CHECK-LABEL: test_svcnot_s16_z: 842; CHECK: // %bb.0: // %entry 843; CHECK-NEXT: mov z0.h, #0 // =0x0 844; CHECK-NEXT: cnot z0.h, p0/m, z1.h 845; CHECK-NEXT: ret 846; 847; CHECK-2p2-LABEL: test_svcnot_s16_z: 848; CHECK-2p2: // %bb.0: // %entry 849; CHECK-2p2-NEXT: cnot z0.h, p0/z, z1.h 850; CHECK-2p2-NEXT: ret 851entry: 852 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 853 ret <vscale x 8 x i16> %0 854} 855 856define <vscale x 4 x i32> @test_svcnot_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) { 857; CHECK-LABEL: test_svcnot_s32_x_1: 858; CHECK: // %bb.0: // %entry 859; CHECK-NEXT: cnot z0.s, p0/m, z0.s 860; CHECK-NEXT: ret 861; 862; CHECK-2p2-LABEL: test_svcnot_s32_x_1: 863; CHECK-2p2: // %bb.0: // %entry 864; CHECK-2p2-NEXT: cnot z0.s, p0/z, z0.s 865; CHECK-2p2-NEXT: ret 866entry: 867 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 868 ret <vscale x 4 x i32> %0 869} 870 871define <vscale x 4 x i32> @test_svcnot_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 872; CHECK-LABEL: test_svcnot_s32_x_2: 873; CHECK: // %bb.0: // %entry 874; CHECK-NEXT: movprfx z0, z1 875; CHECK-NEXT: cnot z0.s, p0/m, z1.s 876; CHECK-NEXT: ret 877; 878; CHECK-2p2-LABEL: test_svcnot_s32_x_2: 879; CHECK-2p2: // %bb.0: // %entry 880; CHECK-2p2-NEXT: cnot z0.s, p0/z, z1.s 881; CHECK-2p2-NEXT: ret 882entry: 883 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 884 ret <vscale x 4 x i32> %0 885} 886 887define <vscale x 4 x i32> @test_svcnot_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 888; CHECK-LABEL: test_svcnot_s32_z: 889; CHECK: // %bb.0: // %entry 890; CHECK-NEXT: mov z0.s, #0 // =0x0 891; CHECK-NEXT: cnot z0.s, p0/m, z1.s 892; CHECK-NEXT: ret 893; 894; CHECK-2p2-LABEL: test_svcnot_s32_z: 895; CHECK-2p2: // %bb.0: // %entry 896; CHECK-2p2-NEXT: cnot z0.s, p0/z, z1.s 897; CHECK-2p2-NEXT: ret 898entry: 899 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 900 ret <vscale x 4 x i32> %0 901} 902 903define <vscale x 2 x i64> @test_svcnot_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) { 904; CHECK-LABEL: test_svcnot_s64_x_1: 905; CHECK: // %bb.0: // %entry 906; CHECK-NEXT: cnot z0.d, p0/m, z0.d 907; CHECK-NEXT: ret 908; 909; CHECK-2p2-LABEL: test_svcnot_s64_x_1: 910; CHECK-2p2: // %bb.0: // %entry 911; CHECK-2p2-NEXT: cnot z0.d, p0/z, z0.d 912; CHECK-2p2-NEXT: ret 913entry: 914 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 915 ret <vscale x 2 x i64> %0 916} 917 918define <vscale x 2 x i64> @test_svcnot_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 919; CHECK-LABEL: test_svcnot_s64_x_2: 920; CHECK: // %bb.0: // %entry 921; CHECK-NEXT: movprfx z0, z1 922; CHECK-NEXT: cnot z0.d, p0/m, z1.d 923; CHECK-NEXT: ret 924; 925; CHECK-2p2-LABEL: test_svcnot_s64_x_2: 926; CHECK-2p2: // %bb.0: // %entry 927; CHECK-2p2-NEXT: cnot z0.d, p0/z, z1.d 928; CHECK-2p2-NEXT: ret 929entry: 930 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 931 ret <vscale x 2 x i64> %0 932} 933 934define <vscale x 2 x i64> @test_svcnot_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 935; CHECK-LABEL: test_svcnot_s64_z: 936; CHECK: // %bb.0: // %entry 937; CHECK-NEXT: mov z0.d, #0 // =0x0 938; CHECK-NEXT: cnot z0.d, p0/m, z1.d 939; CHECK-NEXT: ret 940; 941; CHECK-2p2-LABEL: test_svcnot_s64_z: 942; CHECK-2p2: // %bb.0: // %entry 943; CHECK-2p2-NEXT: cnot z0.d, p0/z, z1.d 944; CHECK-2p2-NEXT: ret 945entry: 946 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 947 ret <vscale x 2 x i64> %0 948} 949 950define <vscale x 16 x i8> @test_svnot_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) { 951; CHECK-LABEL: test_svnot_s8_x_1: 952; CHECK: // %bb.0: // %entry 953; CHECK-NEXT: not z0.b, p0/m, z0.b 954; CHECK-NEXT: ret 955; 956; CHECK-2p2-LABEL: test_svnot_s8_x_1: 957; CHECK-2p2: // %bb.0: // %entry 958; CHECK-2p2-NEXT: not z0.b, p0/z, z0.b 959; CHECK-2p2-NEXT: ret 960entry: 961 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 962 ret <vscale x 16 x i8> %0 963} 964 965define <vscale x 16 x i8> @test_svnot_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 966; CHECK-LABEL: test_svnot_s8_x_2: 967; CHECK: // %bb.0: // %entry 968; CHECK-NEXT: movprfx z0, z1 969; CHECK-NEXT: not z0.b, p0/m, z1.b 970; CHECK-NEXT: ret 971; 972; CHECK-2p2-LABEL: test_svnot_s8_x_2: 973; CHECK-2p2: // %bb.0: // %entry 974; CHECK-2p2-NEXT: not z0.b, p0/z, z1.b 975; CHECK-2p2-NEXT: ret 976entry: 977 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 978 ret <vscale x 16 x i8> %0 979} 980 981define <vscale x 16 x i8> @test_svnot_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) { 982; CHECK-LABEL: test_svnot_s8_z: 983; CHECK: // %bb.0: // %entry 984; CHECK-NEXT: mov z0.b, #0 // =0x0 985; CHECK-NEXT: not z0.b, p0/m, z1.b 986; CHECK-NEXT: ret 987; 988; CHECK-2p2-LABEL: test_svnot_s8_z: 989; CHECK-2p2: // %bb.0: // %entry 990; CHECK-2p2-NEXT: not z0.b, p0/z, z1.b 991; CHECK-2p2-NEXT: ret 992entry: 993 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 994 ret <vscale x 16 x i8> %0 995} 996 997define <vscale x 8 x i16> @test_svnot_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) { 998; CHECK-LABEL: test_svnot_s16_x_1: 999; CHECK: // %bb.0: // %entry 1000; CHECK-NEXT: not z0.h, p0/m, z0.h 1001; CHECK-NEXT: ret 1002; 1003; CHECK-2p2-LABEL: test_svnot_s16_x_1: 1004; CHECK-2p2: // %bb.0: // %entry 1005; CHECK-2p2-NEXT: not z0.h, p0/z, z0.h 1006; CHECK-2p2-NEXT: ret 1007entry: 1008 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1009 ret <vscale x 8 x i16> %0 1010} 1011 1012define <vscale x 8 x i16> @test_svnot_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 1013; CHECK-LABEL: test_svnot_s16_x_2: 1014; CHECK: // %bb.0: // %entry 1015; CHECK-NEXT: movprfx z0, z1 1016; CHECK-NEXT: not z0.h, p0/m, z1.h 1017; CHECK-NEXT: ret 1018; 1019; CHECK-2p2-LABEL: test_svnot_s16_x_2: 1020; CHECK-2p2: // %bb.0: // %entry 1021; CHECK-2p2-NEXT: not z0.h, p0/z, z1.h 1022; CHECK-2p2-NEXT: ret 1023entry: 1024 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1025 ret <vscale x 8 x i16> %0 1026} 1027 1028define <vscale x 8 x i16> @test_svnot_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) { 1029; CHECK-LABEL: test_svnot_s16_z: 1030; CHECK: // %bb.0: // %entry 1031; CHECK-NEXT: mov z0.h, #0 // =0x0 1032; CHECK-NEXT: not z0.h, p0/m, z1.h 1033; CHECK-NEXT: ret 1034; 1035; CHECK-2p2-LABEL: test_svnot_s16_z: 1036; CHECK-2p2: // %bb.0: // %entry 1037; CHECK-2p2-NEXT: not z0.h, p0/z, z1.h 1038; CHECK-2p2-NEXT: ret 1039entry: 1040 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1041 ret <vscale x 8 x i16> %0 1042} 1043 1044define <vscale x 4 x i32> @test_svnot_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) { 1045; CHECK-LABEL: test_svnot_s32_x_1: 1046; CHECK: // %bb.0: // %entry 1047; CHECK-NEXT: not z0.s, p0/m, z0.s 1048; CHECK-NEXT: ret 1049; 1050; CHECK-2p2-LABEL: test_svnot_s32_x_1: 1051; CHECK-2p2: // %bb.0: // %entry 1052; CHECK-2p2-NEXT: not z0.s, p0/z, z0.s 1053; CHECK-2p2-NEXT: ret 1054entry: 1055 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1056 ret <vscale x 4 x i32> %0 1057} 1058 1059define <vscale x 4 x i32> @test_svnot_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 1060; CHECK-LABEL: test_svnot_s32_x_2: 1061; CHECK: // %bb.0: // %entry 1062; CHECK-NEXT: movprfx z0, z1 1063; CHECK-NEXT: not z0.s, p0/m, z1.s 1064; CHECK-NEXT: ret 1065; 1066; CHECK-2p2-LABEL: test_svnot_s32_x_2: 1067; CHECK-2p2: // %bb.0: // %entry 1068; CHECK-2p2-NEXT: not z0.s, p0/z, z1.s 1069; CHECK-2p2-NEXT: ret 1070entry: 1071 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1072 ret <vscale x 4 x i32> %0 1073} 1074 1075define <vscale x 4 x i32> @test_svnot_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) { 1076; CHECK-LABEL: test_svnot_s32_z: 1077; CHECK: // %bb.0: // %entry 1078; CHECK-NEXT: mov z0.s, #0 // =0x0 1079; CHECK-NEXT: not z0.s, p0/m, z1.s 1080; CHECK-NEXT: ret 1081; 1082; CHECK-2p2-LABEL: test_svnot_s32_z: 1083; CHECK-2p2: // %bb.0: // %entry 1084; CHECK-2p2-NEXT: not z0.s, p0/z, z1.s 1085; CHECK-2p2-NEXT: ret 1086entry: 1087 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1088 ret <vscale x 4 x i32> %0 1089} 1090 1091define <vscale x 2 x i64> @test_svnot_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) { 1092; CHECK-LABEL: test_svnot_s64_x_1: 1093; CHECK: // %bb.0: // %entry 1094; CHECK-NEXT: not z0.d, p0/m, z0.d 1095; CHECK-NEXT: ret 1096; 1097; CHECK-2p2-LABEL: test_svnot_s64_x_1: 1098; CHECK-2p2: // %bb.0: // %entry 1099; CHECK-2p2-NEXT: not z0.d, p0/z, z0.d 1100; CHECK-2p2-NEXT: ret 1101entry: 1102 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1103 ret <vscale x 2 x i64> %0 1104} 1105 1106define <vscale x 2 x i64> @test_svnot_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 1107; CHECK-LABEL: test_svnot_s64_x_2: 1108; CHECK: // %bb.0: // %entry 1109; CHECK-NEXT: movprfx z0, z1 1110; CHECK-NEXT: not z0.d, p0/m, z1.d 1111; CHECK-NEXT: ret 1112; 1113; CHECK-2p2-LABEL: test_svnot_s64_x_2: 1114; CHECK-2p2: // %bb.0: // %entry 1115; CHECK-2p2-NEXT: not z0.d, p0/z, z1.d 1116; CHECK-2p2-NEXT: ret 1117entry: 1118 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1119 ret <vscale x 2 x i64> %0 1120} 1121 1122define <vscale x 2 x i64> @test_svnot_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) { 1123; CHECK-LABEL: test_svnot_s64_z: 1124; CHECK: // %bb.0: // %entry 1125; CHECK-NEXT: mov z0.d, #0 // =0x0 1126; CHECK-NEXT: not z0.d, p0/m, z1.d 1127; CHECK-NEXT: ret 1128; 1129; CHECK-2p2-LABEL: test_svnot_s64_z: 1130; CHECK-2p2: // %bb.0: // %entry 1131; CHECK-2p2-NEXT: not z0.d, p0/z, z1.d 1132; CHECK-2p2-NEXT: ret 1133entry: 1134 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1135 ret <vscale x 2 x i64> %0 1136} 1137 1138define <vscale x 16 x i8> @test_svcls_nxv16i8_ptrue_u(double %z0, <vscale x 16 x i8> %x) { 1139; CHECK-LABEL: test_svcls_nxv16i8_ptrue_u: 1140; CHECK: // %bb.0: // %entry 1141; CHECK-NEXT: ptrue p0.b 1142; CHECK-NEXT: movprfx z0, z1 1143; CHECK-NEXT: cls z0.b, p0/m, z1.b 1144; CHECK-NEXT: ret 1145; 1146; CHECK-2p2-LABEL: test_svcls_nxv16i8_ptrue_u: 1147; CHECK-2p2: // %bb.0: // %entry 1148; CHECK-2p2-NEXT: ptrue p0.b 1149; CHECK-2p2-NEXT: cls z0.b, p0/z, z1.b 1150; CHECK-2p2-NEXT: ret 1151entry: 1152 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1153 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 1154 ret <vscale x 16 x i8> %0 1155} 1156 1157define <vscale x 16 x i8> @test_svcls_nxv16i8_ptrue(double %z0, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) { 1158; CHECK-LABEL: test_svcls_nxv16i8_ptrue: 1159; CHECK: // %bb.0: // %entry 1160; CHECK-NEXT: ptrue p0.b 1161; CHECK-NEXT: movprfx z0, z2 1162; CHECK-NEXT: cls z0.b, p0/m, z2.b 1163; CHECK-NEXT: ret 1164; 1165; CHECK-2p2-LABEL: test_svcls_nxv16i8_ptrue: 1166; CHECK-2p2: // %bb.0: // %entry 1167; CHECK-2p2-NEXT: ptrue p0.b 1168; CHECK-2p2-NEXT: cls z0.b, p0/z, z2.b 1169; CHECK-2p2-NEXT: ret 1170entry: 1171 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1172 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %y) 1173 ret <vscale x 16 x i8> %0 1174} 1175 1176define <vscale x 8 x i16> @test_svcls_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) { 1177; CHECK-LABEL: test_svcls_nxv8i16_ptrue_u: 1178; CHECK: // %bb.0: // %entry 1179; CHECK-NEXT: ptrue p0.h 1180; CHECK-NEXT: movprfx z0, z1 1181; CHECK-NEXT: cls z0.h, p0/m, z1.h 1182; CHECK-NEXT: ret 1183; 1184; CHECK-2p2-LABEL: test_svcls_nxv8i16_ptrue_u: 1185; CHECK-2p2: // %bb.0: // %entry 1186; CHECK-2p2-NEXT: ptrue p0.h 1187; CHECK-2p2-NEXT: cls z0.h, p0/z, z1.h 1188; CHECK-2p2-NEXT: ret 1189entry: 1190 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1191 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1192 ret <vscale x 8 x i16> %0 1193} 1194 1195define <vscale x 8 x i16> @test_svcls_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) { 1196; CHECK-LABEL: test_svcls_nxv8i16_ptrue: 1197; CHECK: // %bb.0: // %entry 1198; CHECK-NEXT: ptrue p0.h 1199; CHECK-NEXT: movprfx z0, z2 1200; CHECK-NEXT: cls z0.h, p0/m, z2.h 1201; CHECK-NEXT: ret 1202; 1203; CHECK-2p2-LABEL: test_svcls_nxv8i16_ptrue: 1204; CHECK-2p2: // %bb.0: // %entry 1205; CHECK-2p2-NEXT: ptrue p0.h 1206; CHECK-2p2-NEXT: cls z0.h, p0/z, z2.h 1207; CHECK-2p2-NEXT: ret 1208entry: 1209 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1210 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y) 1211 ret <vscale x 8 x i16> %0 1212} 1213 1214define <vscale x 4 x i32> @test_svcls_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) { 1215; CHECK-LABEL: test_svcls_nxv4i32_ptrue_u: 1216; CHECK: // %bb.0: // %entry 1217; CHECK-NEXT: ptrue p0.s 1218; CHECK-NEXT: movprfx z0, z1 1219; CHECK-NEXT: cls z0.s, p0/m, z1.s 1220; CHECK-NEXT: ret 1221; 1222; CHECK-2p2-LABEL: test_svcls_nxv4i32_ptrue_u: 1223; CHECK-2p2: // %bb.0: // %entry 1224; CHECK-2p2-NEXT: ptrue p0.s 1225; CHECK-2p2-NEXT: cls z0.s, p0/z, z1.s 1226; CHECK-2p2-NEXT: ret 1227entry: 1228 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1229 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1230 ret <vscale x 4 x i32> %0 1231} 1232 1233define <vscale x 4 x i32> @test_svcls_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 1234; CHECK-LABEL: test_svcls_nxv4i32_ptrue: 1235; CHECK: // %bb.0: // %entry 1236; CHECK-NEXT: ptrue p0.s 1237; CHECK-NEXT: movprfx z0, z2 1238; CHECK-NEXT: cls z0.s, p0/m, z2.s 1239; CHECK-NEXT: ret 1240; 1241; CHECK-2p2-LABEL: test_svcls_nxv4i32_ptrue: 1242; CHECK-2p2: // %bb.0: // %entry 1243; CHECK-2p2-NEXT: ptrue p0.s 1244; CHECK-2p2-NEXT: cls z0.s, p0/z, z2.s 1245; CHECK-2p2-NEXT: ret 1246entry: 1247 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1248 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y) 1249 ret <vscale x 4 x i32> %0 1250} 1251 1252define <vscale x 2 x i64> @test_svcls_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) { 1253; CHECK-LABEL: test_svcls_nxv2i64_ptrue_u: 1254; CHECK: // %bb.0: // %entry 1255; CHECK-NEXT: ptrue p0.d 1256; CHECK-NEXT: movprfx z0, z1 1257; CHECK-NEXT: cls z0.d, p0/m, z1.d 1258; CHECK-NEXT: ret 1259; 1260; CHECK-2p2-LABEL: test_svcls_nxv2i64_ptrue_u: 1261; CHECK-2p2: // %bb.0: // %entry 1262; CHECK-2p2-NEXT: ptrue p0.d 1263; CHECK-2p2-NEXT: cls z0.d, p0/z, z1.d 1264; CHECK-2p2-NEXT: ret 1265entry: 1266 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1267 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1268 ret <vscale x 2 x i64> %0 1269} 1270 1271define <vscale x 2 x i64> @test_svcls_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) { 1272; CHECK-LABEL: test_svcls_nxv2i64_ptrue: 1273; CHECK: // %bb.0: // %entry 1274; CHECK-NEXT: ptrue p0.d 1275; CHECK-NEXT: movprfx z0, z2 1276; CHECK-NEXT: cls z0.d, p0/m, z2.d 1277; CHECK-NEXT: ret 1278; 1279; CHECK-2p2-LABEL: test_svcls_nxv2i64_ptrue: 1280; CHECK-2p2: // %bb.0: // %entry 1281; CHECK-2p2-NEXT: ptrue p0.d 1282; CHECK-2p2-NEXT: cls z0.d, p0/z, z2.d 1283; CHECK-2p2-NEXT: ret 1284entry: 1285 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1286 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y) 1287 ret <vscale x 2 x i64> %0 1288} 1289 1290define <vscale x 16 x i8> @test_svclz_nxv16i8_ptrue_u(double %z0, <vscale x 16 x i8> %x) { 1291; CHECK-LABEL: test_svclz_nxv16i8_ptrue_u: 1292; CHECK: // %bb.0: // %entry 1293; CHECK-NEXT: ptrue p0.b 1294; CHECK-NEXT: movprfx z0, z1 1295; CHECK-NEXT: clz z0.b, p0/m, z1.b 1296; CHECK-NEXT: ret 1297; 1298; CHECK-2p2-LABEL: test_svclz_nxv16i8_ptrue_u: 1299; CHECK-2p2: // %bb.0: // %entry 1300; CHECK-2p2-NEXT: ptrue p0.b 1301; CHECK-2p2-NEXT: clz z0.b, p0/z, z1.b 1302; CHECK-2p2-NEXT: ret 1303entry: 1304 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1305 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 1306 ret <vscale x 16 x i8> %0 1307} 1308 1309define <vscale x 16 x i8> @test_svclz_nxv16i8_ptrue(double %z0, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) { 1310; CHECK-LABEL: test_svclz_nxv16i8_ptrue: 1311; CHECK: // %bb.0: // %entry 1312; CHECK-NEXT: ptrue p0.b 1313; CHECK-NEXT: movprfx z0, z2 1314; CHECK-NEXT: clz z0.b, p0/m, z2.b 1315; CHECK-NEXT: ret 1316; 1317; CHECK-2p2-LABEL: test_svclz_nxv16i8_ptrue: 1318; CHECK-2p2: // %bb.0: // %entry 1319; CHECK-2p2-NEXT: ptrue p0.b 1320; CHECK-2p2-NEXT: clz z0.b, p0/z, z2.b 1321; CHECK-2p2-NEXT: ret 1322entry: 1323 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1324 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %y) 1325 ret <vscale x 16 x i8> %0 1326} 1327 1328define <vscale x 8 x i16> @test_svclz_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) { 1329; CHECK-LABEL: test_svclz_nxv8i16_ptrue_u: 1330; CHECK: // %bb.0: // %entry 1331; CHECK-NEXT: ptrue p0.h 1332; CHECK-NEXT: movprfx z0, z1 1333; CHECK-NEXT: clz z0.h, p0/m, z1.h 1334; CHECK-NEXT: ret 1335; 1336; CHECK-2p2-LABEL: test_svclz_nxv8i16_ptrue_u: 1337; CHECK-2p2: // %bb.0: // %entry 1338; CHECK-2p2-NEXT: ptrue p0.h 1339; CHECK-2p2-NEXT: clz z0.h, p0/z, z1.h 1340; CHECK-2p2-NEXT: ret 1341entry: 1342 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1343 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1344 ret <vscale x 8 x i16> %0 1345} 1346 1347define <vscale x 8 x i16> @test_svclz_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) { 1348; CHECK-LABEL: test_svclz_nxv8i16_ptrue: 1349; CHECK: // %bb.0: // %entry 1350; CHECK-NEXT: ptrue p0.h 1351; CHECK-NEXT: movprfx z0, z2 1352; CHECK-NEXT: clz z0.h, p0/m, z2.h 1353; CHECK-NEXT: ret 1354; 1355; CHECK-2p2-LABEL: test_svclz_nxv8i16_ptrue: 1356; CHECK-2p2: // %bb.0: // %entry 1357; CHECK-2p2-NEXT: ptrue p0.h 1358; CHECK-2p2-NEXT: clz z0.h, p0/z, z2.h 1359; CHECK-2p2-NEXT: ret 1360entry: 1361 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1362 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y) 1363 ret <vscale x 8 x i16> %0 1364} 1365 1366define <vscale x 4 x i32> @test_svclz_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) { 1367; CHECK-LABEL: test_svclz_nxv4i32_ptrue_u: 1368; CHECK: // %bb.0: // %entry 1369; CHECK-NEXT: ptrue p0.s 1370; CHECK-NEXT: movprfx z0, z1 1371; CHECK-NEXT: clz z0.s, p0/m, z1.s 1372; CHECK-NEXT: ret 1373; 1374; CHECK-2p2-LABEL: test_svclz_nxv4i32_ptrue_u: 1375; CHECK-2p2: // %bb.0: // %entry 1376; CHECK-2p2-NEXT: ptrue p0.s 1377; CHECK-2p2-NEXT: clz z0.s, p0/z, z1.s 1378; CHECK-2p2-NEXT: ret 1379entry: 1380 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1381 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1382 ret <vscale x 4 x i32> %0 1383} 1384 1385define <vscale x 4 x i32> @test_svclz_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 1386; CHECK-LABEL: test_svclz_nxv4i32_ptrue: 1387; CHECK: // %bb.0: // %entry 1388; CHECK-NEXT: ptrue p0.s 1389; CHECK-NEXT: movprfx z0, z2 1390; CHECK-NEXT: clz z0.s, p0/m, z2.s 1391; CHECK-NEXT: ret 1392; 1393; CHECK-2p2-LABEL: test_svclz_nxv4i32_ptrue: 1394; CHECK-2p2: // %bb.0: // %entry 1395; CHECK-2p2-NEXT: ptrue p0.s 1396; CHECK-2p2-NEXT: clz z0.s, p0/z, z2.s 1397; CHECK-2p2-NEXT: ret 1398entry: 1399 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1400 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y) 1401 ret <vscale x 4 x i32> %0 1402} 1403 1404define <vscale x 2 x i64> @test_svclz_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) { 1405; CHECK-LABEL: test_svclz_nxv2i64_ptrue_u: 1406; CHECK: // %bb.0: // %entry 1407; CHECK-NEXT: ptrue p0.d 1408; CHECK-NEXT: movprfx z0, z1 1409; CHECK-NEXT: clz z0.d, p0/m, z1.d 1410; CHECK-NEXT: ret 1411; 1412; CHECK-2p2-LABEL: test_svclz_nxv2i64_ptrue_u: 1413; CHECK-2p2: // %bb.0: // %entry 1414; CHECK-2p2-NEXT: ptrue p0.d 1415; CHECK-2p2-NEXT: clz z0.d, p0/z, z1.d 1416; CHECK-2p2-NEXT: ret 1417entry: 1418 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1419 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1420 ret <vscale x 2 x i64> %0 1421} 1422 1423define <vscale x 2 x i64> @test_svclz_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) { 1424; CHECK-LABEL: test_svclz_nxv2i64_ptrue: 1425; CHECK: // %bb.0: // %entry 1426; CHECK-NEXT: ptrue p0.d 1427; CHECK-NEXT: movprfx z0, z2 1428; CHECK-NEXT: clz z0.d, p0/m, z2.d 1429; CHECK-NEXT: ret 1430; 1431; CHECK-2p2-LABEL: test_svclz_nxv2i64_ptrue: 1432; CHECK-2p2: // %bb.0: // %entry 1433; CHECK-2p2-NEXT: ptrue p0.d 1434; CHECK-2p2-NEXT: clz z0.d, p0/z, z2.d 1435; CHECK-2p2-NEXT: ret 1436entry: 1437 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1438 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y) 1439 ret <vscale x 2 x i64> %0 1440} 1441 1442define <vscale x 16 x i8> @test_svcnt_nxv16i8_ptrue_u(double %z0, <vscale x 16 x i8> %x) { 1443; CHECK-LABEL: test_svcnt_nxv16i8_ptrue_u: 1444; CHECK: // %bb.0: // %entry 1445; CHECK-NEXT: ptrue p0.b 1446; CHECK-NEXT: movprfx z0, z1 1447; CHECK-NEXT: cnt z0.b, p0/m, z1.b 1448; CHECK-NEXT: ret 1449; 1450; CHECK-2p2-LABEL: test_svcnt_nxv16i8_ptrue_u: 1451; CHECK-2p2: // %bb.0: // %entry 1452; CHECK-2p2-NEXT: ptrue p0.b 1453; CHECK-2p2-NEXT: cnt z0.b, p0/z, z1.b 1454; CHECK-2p2-NEXT: ret 1455entry: 1456 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1457 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 1458 ret <vscale x 16 x i8> %0 1459} 1460 1461define <vscale x 16 x i8> @test_svcnt_nxv16i8_ptrue(double %z0, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) { 1462; CHECK-LABEL: test_svcnt_nxv16i8_ptrue: 1463; CHECK: // %bb.0: // %entry 1464; CHECK-NEXT: ptrue p0.b 1465; CHECK-NEXT: movprfx z0, z2 1466; CHECK-NEXT: cnt z0.b, p0/m, z2.b 1467; CHECK-NEXT: ret 1468; 1469; CHECK-2p2-LABEL: test_svcnt_nxv16i8_ptrue: 1470; CHECK-2p2: // %bb.0: // %entry 1471; CHECK-2p2-NEXT: ptrue p0.b 1472; CHECK-2p2-NEXT: cnt z0.b, p0/z, z2.b 1473; CHECK-2p2-NEXT: ret 1474entry: 1475 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1476 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %y) 1477 ret <vscale x 16 x i8> %0 1478} 1479 1480define <vscale x 8 x i16> @test_svcnt_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) { 1481; CHECK-LABEL: test_svcnt_nxv8i16_ptrue_u: 1482; CHECK: // %bb.0: // %entry 1483; CHECK-NEXT: ptrue p0.h 1484; CHECK-NEXT: movprfx z0, z1 1485; CHECK-NEXT: cnt z0.h, p0/m, z1.h 1486; CHECK-NEXT: ret 1487; 1488; CHECK-2p2-LABEL: test_svcnt_nxv8i16_ptrue_u: 1489; CHECK-2p2: // %bb.0: // %entry 1490; CHECK-2p2-NEXT: ptrue p0.h 1491; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 1492; CHECK-2p2-NEXT: ret 1493entry: 1494 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1495 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1496 ret <vscale x 8 x i16> %0 1497} 1498 1499define <vscale x 8 x i16> @test_svcnt_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) { 1500; CHECK-LABEL: test_svcnt_nxv8i16_ptrue: 1501; CHECK: // %bb.0: // %entry 1502; CHECK-NEXT: ptrue p0.h 1503; CHECK-NEXT: movprfx z0, z2 1504; CHECK-NEXT: cnt z0.h, p0/m, z2.h 1505; CHECK-NEXT: ret 1506; 1507; CHECK-2p2-LABEL: test_svcnt_nxv8i16_ptrue: 1508; CHECK-2p2: // %bb.0: // %entry 1509; CHECK-2p2-NEXT: ptrue p0.h 1510; CHECK-2p2-NEXT: cnt z0.h, p0/z, z2.h 1511; CHECK-2p2-NEXT: ret 1512entry: 1513 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1514 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y) 1515 ret <vscale x 8 x i16> %0 1516} 1517 1518define <vscale x 4 x i32> @test_svcnt_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) { 1519; CHECK-LABEL: test_svcnt_nxv4i32_ptrue_u: 1520; CHECK: // %bb.0: // %entry 1521; CHECK-NEXT: ptrue p0.s 1522; CHECK-NEXT: movprfx z0, z1 1523; CHECK-NEXT: cnt z0.s, p0/m, z1.s 1524; CHECK-NEXT: ret 1525; 1526; CHECK-2p2-LABEL: test_svcnt_nxv4i32_ptrue_u: 1527; CHECK-2p2: // %bb.0: // %entry 1528; CHECK-2p2-NEXT: ptrue p0.s 1529; CHECK-2p2-NEXT: cnt z0.s, p0/z, z1.s 1530; CHECK-2p2-NEXT: ret 1531entry: 1532 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1533 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1534 ret <vscale x 4 x i32> %0 1535} 1536 1537define <vscale x 4 x i32> @test_svcnt_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 1538; CHECK-LABEL: test_svcnt_nxv4i32_ptrue: 1539; CHECK: // %bb.0: // %entry 1540; CHECK-NEXT: ptrue p0.s 1541; CHECK-NEXT: movprfx z0, z2 1542; CHECK-NEXT: cnt z0.s, p0/m, z2.s 1543; CHECK-NEXT: ret 1544; 1545; CHECK-2p2-LABEL: test_svcnt_nxv4i32_ptrue: 1546; CHECK-2p2: // %bb.0: // %entry 1547; CHECK-2p2-NEXT: ptrue p0.s 1548; CHECK-2p2-NEXT: cnt z0.s, p0/z, z2.s 1549; CHECK-2p2-NEXT: ret 1550entry: 1551 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1552 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y) 1553 ret <vscale x 4 x i32> %0 1554} 1555 1556define <vscale x 2 x i64> @test_svcnt_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) { 1557; CHECK-LABEL: test_svcnt_nxv2i64_ptrue_u: 1558; CHECK: // %bb.0: // %entry 1559; CHECK-NEXT: ptrue p0.d 1560; CHECK-NEXT: movprfx z0, z1 1561; CHECK-NEXT: cnt z0.d, p0/m, z1.d 1562; CHECK-NEXT: ret 1563; 1564; CHECK-2p2-LABEL: test_svcnt_nxv2i64_ptrue_u: 1565; CHECK-2p2: // %bb.0: // %entry 1566; CHECK-2p2-NEXT: ptrue p0.d 1567; CHECK-2p2-NEXT: cnt z0.d, p0/z, z1.d 1568; CHECK-2p2-NEXT: ret 1569entry: 1570 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1571 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1572 ret <vscale x 2 x i64> %0 1573} 1574 1575define <vscale x 2 x i64> @test_svcnt_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) { 1576; CHECK-LABEL: test_svcnt_nxv2i64_ptrue: 1577; CHECK: // %bb.0: // %entry 1578; CHECK-NEXT: ptrue p0.d 1579; CHECK-NEXT: movprfx z0, z2 1580; CHECK-NEXT: cnt z0.d, p0/m, z2.d 1581; CHECK-NEXT: ret 1582; 1583; CHECK-2p2-LABEL: test_svcnt_nxv2i64_ptrue: 1584; CHECK-2p2: // %bb.0: // %entry 1585; CHECK-2p2-NEXT: ptrue p0.d 1586; CHECK-2p2-NEXT: cnt z0.d, p0/z, z2.d 1587; CHECK-2p2-NEXT: ret 1588entry: 1589 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1590 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y) 1591 ret <vscale x 2 x i64> %0 1592} 1593 1594define <vscale x 8 x i16> @test_svcnt_nxv8f16_ptrue_u(double %z0, <vscale x 8 x half> %x) { 1595; CHECK-LABEL: test_svcnt_nxv8f16_ptrue_u: 1596; CHECK: // %bb.0: // %entry 1597; CHECK-NEXT: ptrue p0.h 1598; CHECK-NEXT: movprfx z0, z1 1599; CHECK-NEXT: cnt z0.h, p0/m, z1.h 1600; CHECK-NEXT: ret 1601; 1602; CHECK-2p2-LABEL: test_svcnt_nxv8f16_ptrue_u: 1603; CHECK-2p2: // %bb.0: // %entry 1604; CHECK-2p2-NEXT: ptrue p0.h 1605; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 1606; CHECK-2p2-NEXT: ret 1607entry: 1608 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1609 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x) 1610 ret <vscale x 8 x i16> %0 1611} 1612 1613define <vscale x 8 x i16> @test_svcnt_nxv8f16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x half> %y) { 1614; CHECK-LABEL: test_svcnt_nxv8f16_ptrue: 1615; CHECK: // %bb.0: // %entry 1616; CHECK-NEXT: ptrue p0.h 1617; CHECK-NEXT: movprfx z0, z2 1618; CHECK-NEXT: cnt z0.h, p0/m, z2.h 1619; CHECK-NEXT: ret 1620; 1621; CHECK-2p2-LABEL: test_svcnt_nxv8f16_ptrue: 1622; CHECK-2p2: // %bb.0: // %entry 1623; CHECK-2p2-NEXT: ptrue p0.h 1624; CHECK-2p2-NEXT: cnt z0.h, p0/z, z2.h 1625; CHECK-2p2-NEXT: ret 1626entry: 1627 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1628 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x half> %y) 1629 ret <vscale x 8 x i16> %0 1630} 1631 1632define <vscale x 8 x i16> @test_svcnt_nxv8bf16_ptrue_u(double %z0, <vscale x 8 x bfloat> %x) { 1633; CHECK-LABEL: test_svcnt_nxv8bf16_ptrue_u: 1634; CHECK: // %bb.0: // %entry 1635; CHECK-NEXT: ptrue p0.h 1636; CHECK-NEXT: movprfx z0, z1 1637; CHECK-NEXT: cnt z0.h, p0/m, z1.h 1638; CHECK-NEXT: ret 1639; 1640; CHECK-2p2-LABEL: test_svcnt_nxv8bf16_ptrue_u: 1641; CHECK-2p2: // %bb.0: // %entry 1642; CHECK-2p2-NEXT: ptrue p0.h 1643; CHECK-2p2-NEXT: cnt z0.h, p0/z, z1.h 1644; CHECK-2p2-NEXT: ret 1645entry: 1646 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1647 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %x) 1648 ret <vscale x 8 x i16> %0 1649} 1650 1651define <vscale x 8 x i16> @test_svcnt_nxv8bf16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x bfloat> %y) { 1652; CHECK-LABEL: test_svcnt_nxv8bf16_ptrue: 1653; CHECK: // %bb.0: // %entry 1654; CHECK-NEXT: ptrue p0.h 1655; CHECK-NEXT: movprfx z0, z2 1656; CHECK-NEXT: cnt z0.h, p0/m, z2.h 1657; CHECK-NEXT: ret 1658; 1659; CHECK-2p2-LABEL: test_svcnt_nxv8bf16_ptrue: 1660; CHECK-2p2: // %bb.0: // %entry 1661; CHECK-2p2-NEXT: ptrue p0.h 1662; CHECK-2p2-NEXT: cnt z0.h, p0/z, z2.h 1663; CHECK-2p2-NEXT: ret 1664entry: 1665 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1666 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %y) 1667 ret <vscale x 8 x i16> %0 1668} 1669 1670define <vscale x 4 x i32> @test_svcnt_nxv4f32_ptrue_u(double %z0, <vscale x 4 x float> %x) { 1671; CHECK-LABEL: test_svcnt_nxv4f32_ptrue_u: 1672; CHECK: // %bb.0: // %entry 1673; CHECK-NEXT: ptrue p0.s 1674; CHECK-NEXT: movprfx z0, z1 1675; CHECK-NEXT: cnt z0.s, p0/m, z1.s 1676; CHECK-NEXT: ret 1677; 1678; CHECK-2p2-LABEL: test_svcnt_nxv4f32_ptrue_u: 1679; CHECK-2p2: // %bb.0: // %entry 1680; CHECK-2p2-NEXT: ptrue p0.s 1681; CHECK-2p2-NEXT: cnt z0.s, p0/z, z1.s 1682; CHECK-2p2-NEXT: ret 1683entry: 1684 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1685 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x) 1686 ret <vscale x 4 x i32> %0 1687} 1688 1689define <vscale x 4 x i32> @test_svcnt_nxv4f32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x float> %y) { 1690; CHECK-LABEL: test_svcnt_nxv4f32_ptrue: 1691; CHECK: // %bb.0: // %entry 1692; CHECK-NEXT: ptrue p0.s 1693; CHECK-NEXT: movprfx z0, z2 1694; CHECK-NEXT: cnt z0.s, p0/m, z2.s 1695; CHECK-NEXT: ret 1696; 1697; CHECK-2p2-LABEL: test_svcnt_nxv4f32_ptrue: 1698; CHECK-2p2: // %bb.0: // %entry 1699; CHECK-2p2-NEXT: ptrue p0.s 1700; CHECK-2p2-NEXT: cnt z0.s, p0/z, z2.s 1701; CHECK-2p2-NEXT: ret 1702entry: 1703 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1704 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x float> %y) 1705 ret <vscale x 4 x i32> %0 1706} 1707 1708define <vscale x 2 x i64> @test_svcnt_nxv2f64_ptrue_u(double %z0, <vscale x 2 x double> %x) { 1709; CHECK-LABEL: test_svcnt_nxv2f64_ptrue_u: 1710; CHECK: // %bb.0: // %entry 1711; CHECK-NEXT: ptrue p0.d 1712; CHECK-NEXT: movprfx z0, z1 1713; CHECK-NEXT: cnt z0.d, p0/m, z1.d 1714; CHECK-NEXT: ret 1715; 1716; CHECK-2p2-LABEL: test_svcnt_nxv2f64_ptrue_u: 1717; CHECK-2p2: // %bb.0: // %entry 1718; CHECK-2p2-NEXT: ptrue p0.d 1719; CHECK-2p2-NEXT: cnt z0.d, p0/z, z1.d 1720; CHECK-2p2-NEXT: ret 1721entry: 1722 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1723 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x) 1724 ret <vscale x 2 x i64> %0 1725} 1726 1727define <vscale x 2 x i64> @test_svcnt_nxv2f64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x double> %y) { 1728; CHECK-LABEL: test_svcnt_nxv2f64_ptrue: 1729; CHECK: // %bb.0: // %entry 1730; CHECK-NEXT: ptrue p0.d 1731; CHECK-NEXT: movprfx z0, z2 1732; CHECK-NEXT: cnt z0.d, p0/m, z2.d 1733; CHECK-NEXT: ret 1734; 1735; CHECK-2p2-LABEL: test_svcnt_nxv2f64_ptrue: 1736; CHECK-2p2: // %bb.0: // %entry 1737; CHECK-2p2-NEXT: ptrue p0.d 1738; CHECK-2p2-NEXT: cnt z0.d, p0/z, z2.d 1739; CHECK-2p2-NEXT: ret 1740entry: 1741 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1742 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y) 1743 ret <vscale x 2 x i64> %0 1744} 1745 1746define <vscale x 16 x i8> @test_svcnot_nxv16i8_ptrue_u(double %z0, <vscale x 16 x i8> %x) { 1747; CHECK-LABEL: test_svcnot_nxv16i8_ptrue_u: 1748; CHECK: // %bb.0: // %entry 1749; CHECK-NEXT: ptrue p0.b 1750; CHECK-NEXT: movprfx z0, z1 1751; CHECK-NEXT: cnot z0.b, p0/m, z1.b 1752; CHECK-NEXT: ret 1753; 1754; CHECK-2p2-LABEL: test_svcnot_nxv16i8_ptrue_u: 1755; CHECK-2p2: // %bb.0: // %entry 1756; CHECK-2p2-NEXT: ptrue p0.b 1757; CHECK-2p2-NEXT: cnot z0.b, p0/z, z1.b 1758; CHECK-2p2-NEXT: ret 1759entry: 1760 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1761 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 1762 ret <vscale x 16 x i8> %0 1763} 1764 1765define <vscale x 16 x i8> @test_svcnot_nxv16i8_ptrue(double %z0, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) { 1766; CHECK-LABEL: test_svcnot_nxv16i8_ptrue: 1767; CHECK: // %bb.0: // %entry 1768; CHECK-NEXT: ptrue p0.b 1769; CHECK-NEXT: movprfx z0, z2 1770; CHECK-NEXT: cnot z0.b, p0/m, z2.b 1771; CHECK-NEXT: ret 1772; 1773; CHECK-2p2-LABEL: test_svcnot_nxv16i8_ptrue: 1774; CHECK-2p2: // %bb.0: // %entry 1775; CHECK-2p2-NEXT: ptrue p0.b 1776; CHECK-2p2-NEXT: cnot z0.b, p0/z, z2.b 1777; CHECK-2p2-NEXT: ret 1778entry: 1779 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1780 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %y) 1781 ret <vscale x 16 x i8> %0 1782} 1783 1784define <vscale x 8 x i16> @test_svcnot_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) { 1785; CHECK-LABEL: test_svcnot_nxv8i16_ptrue_u: 1786; CHECK: // %bb.0: // %entry 1787; CHECK-NEXT: ptrue p0.h 1788; CHECK-NEXT: movprfx z0, z1 1789; CHECK-NEXT: cnot z0.h, p0/m, z1.h 1790; CHECK-NEXT: ret 1791; 1792; CHECK-2p2-LABEL: test_svcnot_nxv8i16_ptrue_u: 1793; CHECK-2p2: // %bb.0: // %entry 1794; CHECK-2p2-NEXT: ptrue p0.h 1795; CHECK-2p2-NEXT: cnot z0.h, p0/z, z1.h 1796; CHECK-2p2-NEXT: ret 1797entry: 1798 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1799 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1800 ret <vscale x 8 x i16> %0 1801} 1802 1803define <vscale x 8 x i16> @test_svcnot_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) { 1804; CHECK-LABEL: test_svcnot_nxv8i16_ptrue: 1805; CHECK: // %bb.0: // %entry 1806; CHECK-NEXT: ptrue p0.h 1807; CHECK-NEXT: movprfx z0, z2 1808; CHECK-NEXT: cnot z0.h, p0/m, z2.h 1809; CHECK-NEXT: ret 1810; 1811; CHECK-2p2-LABEL: test_svcnot_nxv8i16_ptrue: 1812; CHECK-2p2: // %bb.0: // %entry 1813; CHECK-2p2-NEXT: ptrue p0.h 1814; CHECK-2p2-NEXT: cnot z0.h, p0/z, z2.h 1815; CHECK-2p2-NEXT: ret 1816entry: 1817 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1818 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y) 1819 ret <vscale x 8 x i16> %0 1820} 1821 1822define <vscale x 4 x i32> @test_svcnot_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) { 1823; CHECK-LABEL: test_svcnot_nxv4i32_ptrue_u: 1824; CHECK: // %bb.0: // %entry 1825; CHECK-NEXT: ptrue p0.s 1826; CHECK-NEXT: movprfx z0, z1 1827; CHECK-NEXT: cnot z0.s, p0/m, z1.s 1828; CHECK-NEXT: ret 1829; 1830; CHECK-2p2-LABEL: test_svcnot_nxv4i32_ptrue_u: 1831; CHECK-2p2: // %bb.0: // %entry 1832; CHECK-2p2-NEXT: ptrue p0.s 1833; CHECK-2p2-NEXT: cnot z0.s, p0/z, z1.s 1834; CHECK-2p2-NEXT: ret 1835entry: 1836 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1837 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1838 ret <vscale x 4 x i32> %0 1839} 1840 1841define <vscale x 4 x i32> @test_svcnot_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 1842; CHECK-LABEL: test_svcnot_nxv4i32_ptrue: 1843; CHECK: // %bb.0: // %entry 1844; CHECK-NEXT: ptrue p0.s 1845; CHECK-NEXT: movprfx z0, z2 1846; CHECK-NEXT: cnot z0.s, p0/m, z2.s 1847; CHECK-NEXT: ret 1848; 1849; CHECK-2p2-LABEL: test_svcnot_nxv4i32_ptrue: 1850; CHECK-2p2: // %bb.0: // %entry 1851; CHECK-2p2-NEXT: ptrue p0.s 1852; CHECK-2p2-NEXT: cnot z0.s, p0/z, z2.s 1853; CHECK-2p2-NEXT: ret 1854entry: 1855 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1856 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y) 1857 ret <vscale x 4 x i32> %0 1858} 1859 1860define <vscale x 2 x i64> @test_svcnot_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) { 1861; CHECK-LABEL: test_svcnot_nxv2i64_ptrue_u: 1862; CHECK: // %bb.0: // %entry 1863; CHECK-NEXT: ptrue p0.d 1864; CHECK-NEXT: movprfx z0, z1 1865; CHECK-NEXT: cnot z0.d, p0/m, z1.d 1866; CHECK-NEXT: ret 1867; 1868; CHECK-2p2-LABEL: test_svcnot_nxv2i64_ptrue_u: 1869; CHECK-2p2: // %bb.0: // %entry 1870; CHECK-2p2-NEXT: ptrue p0.d 1871; CHECK-2p2-NEXT: cnot z0.d, p0/z, z1.d 1872; CHECK-2p2-NEXT: ret 1873entry: 1874 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1875 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 1876 ret <vscale x 2 x i64> %0 1877} 1878 1879define <vscale x 2 x i64> @test_svcnot_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) { 1880; CHECK-LABEL: test_svcnot_nxv2i64_ptrue: 1881; CHECK: // %bb.0: // %entry 1882; CHECK-NEXT: ptrue p0.d 1883; CHECK-NEXT: movprfx z0, z2 1884; CHECK-NEXT: cnot z0.d, p0/m, z2.d 1885; CHECK-NEXT: ret 1886; 1887; CHECK-2p2-LABEL: test_svcnot_nxv2i64_ptrue: 1888; CHECK-2p2: // %bb.0: // %entry 1889; CHECK-2p2-NEXT: ptrue p0.d 1890; CHECK-2p2-NEXT: cnot z0.d, p0/z, z2.d 1891; CHECK-2p2-NEXT: ret 1892entry: 1893 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 1894 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y) 1895 ret <vscale x 2 x i64> %0 1896} 1897 1898define <vscale x 16 x i8> @test_svnot_nxv16i8_ptrue_u(double %z0, <vscale x 16 x i8> %x) { 1899; CHECK-LABEL: test_svnot_nxv16i8_ptrue_u: 1900; CHECK: // %bb.0: // %entry 1901; CHECK-NEXT: ptrue p0.b 1902; CHECK-NEXT: movprfx z0, z1 1903; CHECK-NEXT: not z0.b, p0/m, z1.b 1904; CHECK-NEXT: ret 1905; 1906; CHECK-2p2-LABEL: test_svnot_nxv16i8_ptrue_u: 1907; CHECK-2p2: // %bb.0: // %entry 1908; CHECK-2p2-NEXT: ptrue p0.b 1909; CHECK-2p2-NEXT: not z0.b, p0/z, z1.b 1910; CHECK-2p2-NEXT: ret 1911entry: 1912 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1913 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) 1914 ret <vscale x 16 x i8> %0 1915} 1916 1917define <vscale x 16 x i8> @test_svnot_nxv16i8_ptrue(double %z0, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) { 1918; CHECK-LABEL: test_svnot_nxv16i8_ptrue: 1919; CHECK: // %bb.0: // %entry 1920; CHECK-NEXT: ptrue p0.b 1921; CHECK-NEXT: movprfx z0, z2 1922; CHECK-NEXT: not z0.b, p0/m, z2.b 1923; CHECK-NEXT: ret 1924; 1925; CHECK-2p2-LABEL: test_svnot_nxv16i8_ptrue: 1926; CHECK-2p2: // %bb.0: // %entry 1927; CHECK-2p2-NEXT: ptrue p0.b 1928; CHECK-2p2-NEXT: not z0.b, p0/z, z2.b 1929; CHECK-2p2-NEXT: ret 1930entry: 1931 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) 1932 %0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %y) 1933 ret <vscale x 16 x i8> %0 1934} 1935 1936define <vscale x 8 x i16> @test_svnot_nxv8i16_ptrue_u(double %z0, <vscale x 8 x i16> %x) { 1937; CHECK-LABEL: test_svnot_nxv8i16_ptrue_u: 1938; CHECK: // %bb.0: // %entry 1939; CHECK-NEXT: ptrue p0.h 1940; CHECK-NEXT: movprfx z0, z1 1941; CHECK-NEXT: not z0.h, p0/m, z1.h 1942; CHECK-NEXT: ret 1943; 1944; CHECK-2p2-LABEL: test_svnot_nxv8i16_ptrue_u: 1945; CHECK-2p2: // %bb.0: // %entry 1946; CHECK-2p2-NEXT: ptrue p0.h 1947; CHECK-2p2-NEXT: not z0.h, p0/z, z1.h 1948; CHECK-2p2-NEXT: ret 1949entry: 1950 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1951 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) 1952 ret <vscale x 8 x i16> %0 1953} 1954 1955define <vscale x 8 x i16> @test_svnot_nxv8i16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) { 1956; CHECK-LABEL: test_svnot_nxv8i16_ptrue: 1957; CHECK: // %bb.0: // %entry 1958; CHECK-NEXT: ptrue p0.h 1959; CHECK-NEXT: movprfx z0, z2 1960; CHECK-NEXT: not z0.h, p0/m, z2.h 1961; CHECK-NEXT: ret 1962; 1963; CHECK-2p2-LABEL: test_svnot_nxv8i16_ptrue: 1964; CHECK-2p2: // %bb.0: // %entry 1965; CHECK-2p2-NEXT: ptrue p0.h 1966; CHECK-2p2-NEXT: not z0.h, p0/z, z2.h 1967; CHECK-2p2-NEXT: ret 1968entry: 1969 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) 1970 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %y) 1971 ret <vscale x 8 x i16> %0 1972} 1973 1974define <vscale x 4 x i32> @test_svnot_nxv4i32_ptrue_u(double %z0, <vscale x 4 x i32> %x) { 1975; CHECK-LABEL: test_svnot_nxv4i32_ptrue_u: 1976; CHECK: // %bb.0: // %entry 1977; CHECK-NEXT: ptrue p0.s 1978; CHECK-NEXT: movprfx z0, z1 1979; CHECK-NEXT: not z0.s, p0/m, z1.s 1980; CHECK-NEXT: ret 1981; 1982; CHECK-2p2-LABEL: test_svnot_nxv4i32_ptrue_u: 1983; CHECK-2p2: // %bb.0: // %entry 1984; CHECK-2p2-NEXT: ptrue p0.s 1985; CHECK-2p2-NEXT: not z0.s, p0/z, z1.s 1986; CHECK-2p2-NEXT: ret 1987entry: 1988 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 1989 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) 1990 ret <vscale x 4 x i32> %0 1991} 1992 1993define <vscale x 4 x i32> @test_svnot_nxv4i32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 1994; CHECK-LABEL: test_svnot_nxv4i32_ptrue: 1995; CHECK: // %bb.0: // %entry 1996; CHECK-NEXT: ptrue p0.s 1997; CHECK-NEXT: movprfx z0, z2 1998; CHECK-NEXT: not z0.s, p0/m, z2.s 1999; CHECK-NEXT: ret 2000; 2001; CHECK-2p2-LABEL: test_svnot_nxv4i32_ptrue: 2002; CHECK-2p2: // %bb.0: // %entry 2003; CHECK-2p2-NEXT: ptrue p0.s 2004; CHECK-2p2-NEXT: not z0.s, p0/z, z2.s 2005; CHECK-2p2-NEXT: ret 2006entry: 2007 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) 2008 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %y) 2009 ret <vscale x 4 x i32> %0 2010} 2011 2012define <vscale x 2 x i64> @test_svnot_nxv2i64_ptrue_u(double %z0, <vscale x 2 x i64> %x) { 2013; CHECK-LABEL: test_svnot_nxv2i64_ptrue_u: 2014; CHECK: // %bb.0: // %entry 2015; CHECK-NEXT: ptrue p0.d 2016; CHECK-NEXT: movprfx z0, z1 2017; CHECK-NEXT: not z0.d, p0/m, z1.d 2018; CHECK-NEXT: ret 2019; 2020; CHECK-2p2-LABEL: test_svnot_nxv2i64_ptrue_u: 2021; CHECK-2p2: // %bb.0: // %entry 2022; CHECK-2p2-NEXT: ptrue p0.d 2023; CHECK-2p2-NEXT: not z0.d, p0/z, z1.d 2024; CHECK-2p2-NEXT: ret 2025entry: 2026 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 2027 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) 2028 ret <vscale x 2 x i64> %0 2029} 2030 2031define <vscale x 2 x i64> @test_svnot_nxv2i64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x i64> %y) { 2032; CHECK-LABEL: test_svnot_nxv2i64_ptrue: 2033; CHECK: // %bb.0: // %entry 2034; CHECK-NEXT: ptrue p0.d 2035; CHECK-NEXT: movprfx z0, z2 2036; CHECK-NEXT: not z0.d, p0/m, z2.d 2037; CHECK-NEXT: ret 2038; 2039; CHECK-2p2-LABEL: test_svnot_nxv2i64_ptrue: 2040; CHECK-2p2: // %bb.0: // %entry 2041; CHECK-2p2-NEXT: ptrue p0.d 2042; CHECK-2p2-NEXT: not z0.d, p0/z, z2.d 2043; CHECK-2p2-NEXT: ret 2044entry: 2045 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 2046 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %y) 2047 ret <vscale x 2 x i64> %0 2048} 2049