xref: /llvm-project/llvm/test/CodeGen/AArch64/zero-reg.ll (revision 1ee315ae7964c8433b772e0b5d667834994ba753)
1; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
2
3@var32 = dso_local global i32 0
4@var64 = dso_local global i64 0
5
6define dso_local void @test_zr() {
7; CHECK-LABEL: test_zr:
8
9  store i32 0, ptr @var32
10; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32]
11  store i64 0, ptr @var64
12; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64]
13
14  ret void
15; CHECK: ret
16}
17
18define dso_local void @test_sp(i32 %val) {
19; CHECK-LABEL: test_sp:
20
21; Important correctness point here is that LLVM doesn't try to use xzr
22; as an addressing register: "str w0, [xzr]" is not a valid A64
23; instruction (0b11111 in the Rn field would mean "sp").
24  %addr = getelementptr i32, ptr null, i64 0
25  store i32 %val, ptr %addr
26; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}]
27
28  ret void
29; CHECK: ret
30}
31