1; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s 2 3define i64 @sbfiz64(i64 %v) { 4; CHECK-LABEL: sbfiz64: 5; CHECK: sbfiz x0, x0, #1, #16 6 %shl = shl i64 %v, 48 7 %shr = ashr i64 %shl, 47 8 ret i64 %shr 9} 10 11define i32 @sbfiz32(i32 %v) { 12; CHECK-LABEL: sbfiz32: 13; CHECK: sbfiz w0, w0, #1, #14 14 %shl = shl i32 %v, 18 15 %shr = ashr i32 %shl, 17 16 ret i32 %shr 17} 18 19define i64 @ubfiz64(i64 %v) { 20; CHECK-LABEL: ubfiz64: 21; CHECK: ubfiz x0, x0, #36, #11 22 %shl = shl i64 %v, 53 23 %shr = lshr i64 %shl, 17 24 ret i64 %shr 25} 26 27define i32 @ubfiz32(i32 %v) { 28; CHECK-LABEL: ubfiz32: 29; CHECK: ubfiz w0, w0, #6, #24 30 %shl = shl i32 %v, 8 31 %shr = lshr i32 %shl, 2 32 ret i32 %shr 33} 34 35define i64 @ubfiz64and(i64 %v) { 36; CHECK-LABEL: ubfiz64and: 37; CHECK: ubfiz x0, x0, #36, #11 38 %shl = shl i64 %v, 36 39 %and = and i64 %shl, 140668768878592 40 ret i64 %and 41} 42 43define i32 @ubfiz32and(i32 %v) { 44; CHECK-LABEL: ubfiz32and: 45; CHECK: ubfiz w0, w0, #6, #24 46 %shl = shl i32 %v, 6 47 %and = and i32 %shl, 1073741760 48 ret i32 %and 49} 50 51; Check that we don't generate a ubfiz if the lsl has more than one 52; use, since we'd just be replacing an and with a ubfiz. 53define i32 @noubfiz32(i32 %v) { 54; CHECK-LABEL: noubfiz32: 55; CHECK: lsl w[[REG1:[0-9]+]], w0, #6 56; CHECK: and w[[REG2:[0-9]+]], w[[REG1]], #0x3fffffc0 57; CHECK: add w0, w[[REG1]], w[[REG2]] 58; CHECK: ret 59 %shl = shl i32 %v, 6 60 %and = and i32 %shl, 1073741760 61 %add = add i32 %shl, %and 62 ret i32 %add 63} 64 65define i64 @lsl32_not_ubfiz64(i64 %v) { 66; CHECK-LABEL: lsl32_not_ubfiz64: 67; CHECK: lsl w0, w0, #6 68 %shl = shl i64 %v, 6 69 %and = and i64 %shl, 4294967295 70 ret i64 %and 71} 72 73define i64 @lsl_zext_i8_i64(i8 %b) { 74; CHECK-LABEL: lsl_zext_i8_i64: 75; CHECK: ubfiz x0, x0, #1, #8 76 %1 = zext i8 %b to i64 77 %2 = shl i64 %1, 1 78 ret i64 %2 79} 80 81define i64 @lsl_zext_i16_i64(i16 %b) { 82; CHECK-LABEL: lsl_zext_i16_i64: 83; CHECK: ubfiz x0, x0, #1, #16 84 %1 = zext i16 %b to i64 85 %2 = shl i64 %1, 1 86 ret i64 %2 87} 88 89; Regression test for: 90; https://github.com/llvm/llvm-project/pull/118974#issuecomment-2598521878 91; that exposed infinite loop in DAGCombiner. 92define void @_f(ptr %0, ptr %1, i64 %2) { 93; CHECK-LABEL: @_f 94; CHECK-NOT: ubfiz 95 store i64 -2401053089408754003, ptr %1, align 8 96 %4 = and i64 %2, -2401053089408754003 97 %5 = shl i64 %4, 1 98 store i64 %5, ptr %0, align 1 99 %6 = lshr i64 %4, 54 100 %7 = shl i64 %2, 10 101 %8 = and i64 %7, 131072 102 %9 = or i64 %8, %6 103 store i64 %9, ptr %1, align 1 104 ret void 105} 106