xref: /llvm-project/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll (revision d39b4ce3ce8a3c256e01bdec2b140777a332a633) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
3
4define i64 @vscale_lshr(i64 %TC) {
5; CHECK-LABEL: vscale_lshr:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    rdvl x8, #1
8; CHECK-NEXT:    lsr x8, x8, #4
9; CHECK-NEXT:    lsr x8, x8, #3
10; CHECK-NEXT:    sub x8, x8, #1
11; CHECK-NEXT:    and x0, x0, x8
12; CHECK-NEXT:    ret
13  %vscale = call i64 @llvm.vscale.i64()
14  %shifted = lshr i64 %vscale, 3
15  %urem = urem i64 %TC, %shifted
16  ret i64 %urem
17}
18
19define i64 @vscale(i64 %TC) {
20; CHECK-LABEL: vscale:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    rdvl x8, #1
23; CHECK-NEXT:    lsr x8, x8, #4
24; CHECK-NEXT:    sub x8, x8, #1
25; CHECK-NEXT:    and x0, x0, x8
26; CHECK-NEXT:    ret
27  %vscale = call i64 @llvm.vscale.i64()
28  %urem = urem i64 %TC, %vscale
29  ret i64 %urem
30}
31
32define i64 @vscale_shl(i64 %TC) {
33; CHECK-LABEL: vscale_shl:
34; CHECK:       // %bb.0:
35; CHECK-NEXT:    cnth x8
36; CHECK-NEXT:    sub x8, x8, #1
37; CHECK-NEXT:    and x0, x0, x8
38; CHECK-NEXT:    ret
39  %vscale = call i64 @llvm.vscale.i64()
40  %shifted = shl i64 %vscale, 3
41  %urem = urem i64 %TC, %shifted
42  ret i64 %urem
43}
44
45declare i64 @llvm.vscale.i64()
46